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gpu: nvgpu: Bump FB gk20a code to gm20b
Move all code from fb_gk20a.c to fb_gm20b.c. Change-Id: I87fbdfee76599e019564d66bf248aaffcf978498 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801422 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,124 +0,0 @@
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/*
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* GK20A memory interface
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <trace/events/gk20a.h>
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#include "gk20a/gk20a.h"
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#include "fb_gk20a.h"
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#include <nvgpu/timers.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
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void fb_gk20a_reset(struct gk20a *g)
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{
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u32 val;
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nvgpu_log_info(g, "reset gk20a fb");
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val = gk20a_readl(g, mc_elpg_enable_r());
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val |= mc_elpg_enable_xbar_enabled_f()
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| mc_elpg_enable_pfb_enabled_f()
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| mc_elpg_enable_hub_enabled_f();
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gk20a_writel(g, mc_elpg_enable_r(), val);
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}
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void gk20a_fb_init_hw(struct gk20a *g)
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{
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u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
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gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
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}
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void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
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{
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struct nvgpu_timeout timeout;
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u32 addr_lo;
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u32 data;
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nvgpu_log_fn(g, " ");
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/* pagetables are considered sw states which are preserved after
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prepare_poweroff. When gk20a deinit releases those pagetables,
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common code in vm unmap path calls tlb invalidate that touches
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hw. Use the power_on flag to skip tlb invalidation when gpu
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power is turned off */
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if (!g->power_on) {
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return;
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}
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addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12);
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nvgpu_mutex_acquire(&g->mm.tlb_lock);
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trace_gk20a_mm_tlb_invalidate(g->name);
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) {
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break;
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}
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu fifo space"));
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if (nvgpu_timeout_peek_expired(&timeout)) {
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goto out;
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}
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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gk20a_writel(g, fb_mmu_invalidate_pdb_r(),
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fb_mmu_invalidate_pdb_addr_f(addr_lo) |
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nvgpu_aperture_mask(g, pdb,
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_vid_mem_f()));
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gk20a_writel(g, fb_mmu_invalidate_r(),
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fb_mmu_invalidate_all_va_true_f() |
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fb_mmu_invalidate_trigger_true_f());
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_empty_v(data) !=
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fb_mmu_ctrl_pri_fifo_empty_false_f()) {
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break;
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}
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu invalidate"));
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trace_gk20a_mm_tlb_invalidate_done(g->name);
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out:
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nvgpu_mutex_release(&g->mm.tlb_lock);
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}
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@@ -1,33 +0,0 @@
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/*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FB_GK20A_H
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#define FB_GK20A_H
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struct gk20a;
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struct nvgpu_mem;
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void fb_gk20a_reset(struct gk20a *g);
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void gk20a_fb_init_hw(struct gk20a *g);
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void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
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#endif
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@@ -22,22 +22,112 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <trace/events/gk20a.h>
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#include <nvgpu/sizes.h>
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#include <nvgpu/utils.h>
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#include "gk20a/gk20a.h"
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#include "fb_gk20a.h"
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#include "fb_gm20b.h"
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
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#define VPR_INFO_FETCH_WAIT (5)
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#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
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void gm20b_fb_reset(struct gk20a *g)
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{
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u32 val;
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nvgpu_log_info(g, "reset gk20a fb");
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val = gk20a_readl(g, mc_elpg_enable_r());
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val |= mc_elpg_enable_xbar_enabled_f()
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| mc_elpg_enable_pfb_enabled_f()
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| mc_elpg_enable_hub_enabled_f();
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gk20a_writel(g, mc_elpg_enable_r(), val);
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}
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void gm20b_fb_init_hw(struct gk20a *g)
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{
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u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
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gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
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}
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void gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
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{
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struct nvgpu_timeout timeout;
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u32 addr_lo;
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u32 data;
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nvgpu_log_fn(g, " ");
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/* pagetables are considered sw states which are preserved after
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prepare_poweroff. When gk20a deinit releases those pagetables,
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common code in vm unmap path calls tlb invalidate that touches
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hw. Use the power_on flag to skip tlb invalidation when gpu
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power is turned off */
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if (!g->power_on) {
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return;
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}
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addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12);
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nvgpu_mutex_acquire(&g->mm.tlb_lock);
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trace_gk20a_mm_tlb_invalidate(g->name);
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) {
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break;
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}
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu fifo space"));
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if (nvgpu_timeout_peek_expired(&timeout)) {
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goto out;
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}
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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gk20a_writel(g, fb_mmu_invalidate_pdb_r(),
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fb_mmu_invalidate_pdb_addr_f(addr_lo) |
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nvgpu_aperture_mask(g, pdb,
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_vid_mem_f()));
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gk20a_writel(g, fb_mmu_invalidate_r(),
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fb_mmu_invalidate_all_va_true_f() |
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fb_mmu_invalidate_trigger_true_f());
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_empty_v(data) !=
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fb_mmu_ctrl_pri_fifo_empty_false_f()) {
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break;
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}
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu invalidate"));
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trace_gk20a_mm_tlb_invalidate_done(g->name);
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out:
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nvgpu_mutex_release(&g->mm.tlb_lock);
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}
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void fb_gm20b_init_fs_state(struct gk20a *g)
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{
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nvgpu_log_info(g, "initialize gm20b fb");
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@@ -1,7 +1,7 @@
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/*
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* GM20B FB
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -22,12 +22,18 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _NVHOST_GM20B_FB
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#define _NVHOST_GM20B_FB
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#ifndef NVGPU_FB_GM20B
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#define NVGPU_FB_GM20B
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#include <nvgpu/types.h>
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struct gk20a;
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struct wpr_carveout_info;
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struct nvgpu_mem;
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void gm20b_fb_reset(struct gk20a *g);
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void gm20b_fb_init_hw(struct gk20a *g);
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void gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
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void fb_gm20b_init_fs_state(struct gk20a *g);
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void gm20b_fb_set_mmu_page_size(struct gk20a *g);
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bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g);
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@@ -40,7 +40,7 @@
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#include "gv11b/fifo_gv11b.h"
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#include "gv11b/ce_gv11b.h"
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#include "fb_gk20a.h"
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#include "fb_gm20b.h"
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#include "fb_gp10b.h"
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#include "fb_gv11b.h"
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@@ -64,7 +64,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
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void gv11b_fb_init_hw(struct gk20a *g)
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{
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gk20a_fb_init_hw(g);
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gm20b_fb_init_hw(g);
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g->ops.fb.enable_hub_intr(g);
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}
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