diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_gk20a_fusa.c index a2717aff0..aed503736 100644 --- a/drivers/gpu/nvgpu/hal/fifo/channel_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/channel_gk20a_fusa.c @@ -36,14 +36,14 @@ void gk20a_channel_enable(struct nvgpu_channel *ch) { - gk20a_writel(ch->g, ccsr_channel_r(ch->chid), + nvgpu_writel(ch->g, ccsr_channel_r(ch->chid), gk20a_readl(ch->g, ccsr_channel_r(ch->chid)) | ccsr_channel_enable_set_true_f()); } void gk20a_channel_disable(struct nvgpu_channel *ch) { - gk20a_writel(ch->g, ccsr_channel_r(ch->chid), + nvgpu_writel(ch->g, ccsr_channel_r(ch->chid), gk20a_readl(ch->g, ccsr_channel_r(ch->chid)) | ccsr_channel_enable_clr_true_f()); @@ -72,7 +72,7 @@ static const char * const ccsr_chan_status_str[] = { void gk20a_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *state) { - u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid)); + u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid)); u32 status_v = ccsr_channel_status_v(reg); state->next = ccsr_channel_next_v(reg) == ccsr_channel_next_true_v(); diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 9e041d28e..907b6d713 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -74,6 +74,7 @@ UNITS := \ $(UNIT_SRC)/netlist \ $(UNIT_SRC)/fifo \ $(UNIT_SRC)/fifo/channel \ + $(UNIT_SRC)/fifo/channel/gk20a \ $(UNIT_SRC)/fifo/runlist \ $(UNIT_SRC)/fifo/tsg \ $(UNIT_SRC)/fifo/tsg/gv11b \ diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index bc8ddd2c1..a04bb818a 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -8,6 +8,7 @@ INPUT += ../../../userspace/units/falcon/falcon_tests/nvgpu-falcon.h INPUT += ../../../userspace/units/netlist/nvgpu-netlist.h INPUT += ../../../userspace/units/fifo/nvgpu-fifo.h INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel.h +INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel-gk20a.h INPUT += ../../../userspace/units/fifo/runlist/nvgpu-runlist.h INPUT += ../../../userspace/units/fifo/tsg/nvgpu-tsg.h INPUT += ../../../userspace/units/fifo/tsg/gv11b/nvgpu-tsg-gv11b.h diff --git a/userspace/units/fifo/channel/gk20a/Makefile b/userspace/units/fifo/channel/gk20a/Makefile new file mode 100644 index 000000000..405c4f42d --- /dev/null +++ b/userspace/units/fifo/channel/gk20a/Makefile @@ -0,0 +1,32 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-channel-gk20a.o +MODULE = nvgpu-channel-gk20a + +LIB_PATHS += -lnvgpu-fifo +include ../../../Makefile.units + +lib$(MODULE).so: fifo + +fifo: + $(MAKE) -C ../.. diff --git a/userspace/units/fifo/channel/gk20a/Makefile.interface.tmk b/userspace/units/fifo/channel/gk20a/Makefile.interface.tmk new file mode 100644 index 000000000..faf3cd504 --- /dev/null +++ b/userspace/units/fifo/channel/gk20a/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-channel-gk20a + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/channel/gk20a/Makefile.tmk b/userspace/units/fifo/channel/gk20a/Makefile.tmk new file mode 100644 index 000000000..9aa5b8525 --- /dev/null +++ b/userspace/units/fifo/channel/gk20a/Makefile.tmk @@ -0,0 +1,40 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME = nvgpu-channel-gk20a +NVGPU_UNIT_SRCS = nvgpu-channel-gk20a.c + +NVGPU_UNIT_INTERFACE_DIRS := \ + $(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \ + $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.c b/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.c new file mode 100644 index 000000000..3b155d3e0 --- /dev/null +++ b/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hal/fifo/channel_gk20a.h" +#include + +#include "../../nvgpu-fifo.h" +#include "nvgpu-channel-gk20a.h" + +#ifdef CHANNEL_GK20A_UNIT_DEBUG +#undef unit_verbose +#define unit_verbose unit_info +#else +#define unit_verbose(unit, msg, ...) \ + do { \ + if (0) { \ + unit_info(unit, msg, ##__VA_ARGS__); \ + } \ + } while (0) +#endif + +#define assert(cond) unit_assert(cond, goto done) +#define branches_str test_fifo_flags_str + +int test_gk20a_channel_enable(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + gk20a_channel_enable(ch); + assert((nvgpu_readl(ch->g, ccsr_channel_r(ch->chid)) + & ccsr_channel_enable_set_true_f()) != 0); + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + +int test_gk20a_channel_disable(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + gk20a_channel_disable(ch); + assert((nvgpu_readl(ch->g, ccsr_channel_r(ch->chid)) + & ccsr_channel_enable_clr_true_f()) != 0); + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + + +#define F_CHANNEL_READ_STATE_NEXT BIT(0) +#define F_CHANNEL_READ_STATE_ENABLED BIT(1) +#define F_CHANNEL_READ_STATE_BUSY BIT(2) +#define F_CHANNEL_READ_STATE_LAST BIT(3) + +static const char *f_channel_read_state[] = { + "next", + "enabled", + "busy", +}; + +int test_gk20a_channel_read_state(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + struct nvgpu_channel_hw_state state; + u32 branches; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + for (branches = 0U; branches < F_CHANNEL_READ_STATE_LAST; branches++) { + + u32 v_next = 0; + u32 v_enable = 0; + u32 v_status = 0; + u32 v_busy = 0; + u32 v = 0; + + bool next = false; + bool enabled = false; + bool busy = false; + + if (branches & F_CHANNEL_READ_STATE_NEXT) { + v_next = ccsr_channel_next_true_v(); + next = true; + } + + if (branches & F_CHANNEL_READ_STATE_ENABLED) { + v_enable = ccsr_channel_enable_in_use_v(); + enabled = true; + } + + if (branches & F_CHANNEL_READ_STATE_BUSY) { + v_busy = ccsr_channel_busy_true_v(); + busy = true; + } + + for (v_status = ccsr_channel_status_idle_v(); + v_status <= ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(); + v_status++) { + + bool ctx_reload = false; + bool pending_acquire = false; + + unit_verbose(m, "%s branches=%s v_status=%x\n", + __func__, + branches_str(branches, f_channel_read_state), + v_status); + + switch (v_status) { + case ccsr_channel_status_pending_ctx_reload_v(): + case ccsr_channel_status_pending_acq_ctx_reload_v(): + case ccsr_channel_status_on_pbdma_ctx_reload_v(): + case ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(): + case ccsr_channel_status_on_eng_ctx_reload_v(): + case ccsr_channel_status_on_eng_pending_ctx_reload_v(): + case ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(): + ctx_reload = true; + break; + + case ccsr_channel_status_pending_acquire_v(): + case ccsr_channel_status_on_eng_pending_acquire_v(): + pending_acquire = true; + break; + + default: + break; + } + + v = v_enable << 0U | v_next << 1U | v_status << 24U | v_busy << 28U; + + nvgpu_writel(g, ccsr_channel_r(ch->chid), v); + + gk20a_channel_read_state(g, ch, &state); + + assert(state.next == next); + assert(state.enabled == enabled); + assert(state.busy == busy); + assert(state.ctx_reload == ctx_reload); + assert(state.pending_acquire == pending_acquire); + } + } + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + +struct unit_module_test nvgpu_channel_gk20a_tests[] = { + UNIT_TEST(init_support, test_fifo_init_support, NULL, 0), + UNIT_TEST(enable, test_gk20a_channel_enable, NULL, 0), + UNIT_TEST(disable, test_gk20a_channel_disable, NULL, 0), + UNIT_TEST(read_state, test_gk20a_channel_read_state, NULL, 0), + UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0), +}; + +UNIT_MODULE(nvgpu_channel_gk20a, nvgpu_channel_gk20a_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.h b/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.h new file mode 100644 index 000000000..6214d4b46 --- /dev/null +++ b/userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef UNIT_NVGPU_CHANNEL_GK20A_H +#define UNIT_NVGPU_CHANNEL_GK20A_H + +#include + +struct unit_module; +struct gk20a; + +/** @addtogroup SWUTS-fifo-channel-gk20a + * @{ + * + * Software Unit Test Specification for fifo/channel/gk20a + */ + +/** + * Test specification for: test_gk20a_channel_enable + * + * Description: Branch coverage for gk20a_channel_enable + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel + * - Call gk20a_channel_enable + * - Check that enable_set bit is set for ccsr_channel_r + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gk20a_channel_enable(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_channel_disable + * + * Description: Branch coverage for gk20a_channel_disable + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel + * - Call gk20a_channel_disable + * - Check that enable_clr bit is set for ccsr_channel_r + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gk20a_channel_disable(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_channel_read_state + * + * Description: Branch coverage for gk20a_channel_read_state + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel + * - Build ccsr_channel_r with all combinations of next, enable, + * status and busy fields. + * - Check that interpreted status for next, enabled, busy, ctx_reload + * and pending_acquire are in accordaance with fields read from H/W. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gk20a_channel_read_state(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * @} + */ + +#endif /* UNIT_NVGPU_CHANNEL_GK20A_H */