diff --git a/arch/nvgpu-linux.yaml b/arch/nvgpu-linux.yaml
index 30ce2d3c6..c19dca68f 100644
--- a/arch/nvgpu-linux.yaml
+++ b/arch/nvgpu-linux.yaml
@@ -224,6 +224,7 @@ headers:
              include/nvgpu/linux/dma.h,
              include/nvgpu/linux/kmem.h,
              include/nvgpu/linux/lock.h,
+             include/nvgpu/linux/bitops.h,
              include/nvgpu/linux/nvgpu_mem.h,
              include/nvgpu/linux/os_fence_android.h,
              include/nvgpu/linux/rwsem.h,
diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
index 303d039d9..f417d6c38 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
@@ -367,7 +367,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
 	 * image info and total falcon count
 	 */
 	for (i = 0U; i < FALCON_ID_END; i++) {
-		if (test_bit((int)i, (void *)&acr->lsf_enable_mask) &&
+		if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) &&
 			acr->lsf[i].get_lsf_ucode_details != NULL) {
 
 			(void) memset(&ucode_img, 0, sizeof(ucode_img));
diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
index 452b41029..9234e8baf 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
@@ -477,7 +477,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
 	 * image info and total falcon count
 	 */
 	for (i = 0U; i < FALCON_ID_END; i++) {
-		if (test_bit((int)i, (void *)&acr->lsf_enable_mask) &&
+		if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) &&
 			acr->lsf[i].get_lsf_ucode_details != NULL) {
 
 			(void) memset(&ucode_img, 0, sizeof(ucode_img));
diff --git a/drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c b/drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c
index 45f901844..84e7d23f1 100644
--- a/drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c
+++ b/drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c
@@ -134,7 +134,7 @@ static int engine_fb_queue_set_element_use_state(
 		goto exit;
 	}
 
-	if (test_bit((int)queue_pos,
+	if (nvgpu_test_bit(queue_pos,
 		(void *)&queue->fbq.element_in_use) && set) {
 		nvgpu_err(queue->g,
 			"FBQ last received queue element not processed yet"
@@ -144,9 +144,9 @@ static int engine_fb_queue_set_element_use_state(
 	}
 
 	if (set) {
-		set_bit((int)queue_pos, (void *)&queue->fbq.element_in_use);
+		nvgpu_set_bit(queue_pos, (void *)&queue->fbq.element_in_use);
 	} else {
-		clear_bit((int)queue_pos, (void *)&queue->fbq.element_in_use);
+		nvgpu_clear_bit(queue_pos, (void *)&queue->fbq.element_in_use);
 	}
 
 exit:
@@ -164,7 +164,7 @@ static int engine_fb_queue_is_element_in_use(
 		goto exit;
 	}
 
-	*in_use = test_bit((int)queue_pos, (void *)&queue->fbq.element_in_use);
+	*in_use = nvgpu_test_bit(queue_pos, (void *)&queue->fbq.element_in_use);
 
 exit:
 	return err;
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c
index eab8ecd9d..b9491737c 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist.c
@@ -100,7 +100,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
 	/* add runnable channels bound to this TSG */
 	nvgpu_list_for_each_entry(ch, &tsg->ch_list,
 			nvgpu_channel, ch_entry) {
-		if (!test_bit((int)ch->chid,
+		if (!nvgpu_test_bit(ch->chid,
 			      runlist->active_channels)) {
 			continue;
 		}
@@ -337,24 +337,24 @@ static bool gk20a_runlist_modify_active_locked(struct gk20a *g, u32 runlist_id,
 	}
 
 	if (add) {
-		if (test_and_set_bit((int)ch->chid,
+		if (nvgpu_test_and_set_bit(ch->chid,
 				runlist->active_channels)) {
 			/* was already there */
 			return false;
 		} else {
 			/* new, and belongs to a tsg */
-			set_bit((int)tsg->tsgid, runlist->active_tsgs);
+			nvgpu_set_bit(tsg->tsgid, runlist->active_tsgs);
 			tsg->num_active_channels++;
 		}
 	} else {
-		if (!test_and_clear_bit((int)ch->chid,
+		if (!nvgpu_test_and_clear_bit(ch->chid,
 				runlist->active_channels)) {
 			/* wasn't there */
 			return false;
 		} else {
 			if (--tsg->num_active_channels == 0U) {
 				/* was the only member of this tsg */
-				clear_bit((int)tsg->tsgid,
+				nvgpu_clear_bit(tsg->tsgid,
 						runlist->active_tsgs);
 			}
 		}
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 378c4fd05..55ec0d3b6 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -72,7 +72,7 @@ static bool gk20a_is_channel_active(struct gk20a *g, struct nvgpu_channel *ch)
 
 	for (i = 0; i < f->num_runlists; ++i) {
 		runlist = &f->active_runlist_info[i];
-		if (test_bit((int)ch->chid, runlist->active_channels)) {
+		if (nvgpu_test_bit(ch->chid, runlist->active_channels)) {
 			return true;
 		}
 	}
diff --git a/drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c b/drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c
index 9a9de9b75..2bb7e8501 100644
--- a/drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c
@@ -136,7 +136,7 @@ static void nvgpu_bitmap_free_fixed(struct nvgpu_allocator *na,
 	alloc_lock(na);
 	nvgpu_assert(offs <= U32_MAX);
 	nvgpu_assert(blks <= (u32)INT_MAX);
-	bitmap_clear(a->bitmap, (u32)offs, (int)blks);
+	nvgpu_bitmap_clear(a->bitmap, (u32)offs, (u32)blks);
 	a->bytes_freed += blks * a->blk_size;
 	alloc_unlock(na);
 
@@ -275,7 +275,7 @@ static u64 nvgpu_bitmap_balloc(struct nvgpu_allocator *na, u64 len)
 fail_reset_bitmap:
 	nvgpu_assert(blks <= (u32)INT_MAX);
 	nvgpu_assert(offs <= U32_MAX);
-	bitmap_clear(a->bitmap, (u32)offs, (int)blks);
+	nvgpu_bitmap_clear(a->bitmap, (u32)offs, blks);
 fail:
 	a->next_blk = 0;
 	alloc_unlock(na);
@@ -313,7 +313,7 @@ static void nvgpu_bitmap_free(struct nvgpu_allocator *na, u64 addr)
 
 	nvgpu_assert(blks <= (u32)INT_MAX);
 	nvgpu_assert(offs <= U32_MAX);
-	bitmap_clear(a->bitmap, (u32)offs, (int)blks);
+	nvgpu_bitmap_clear(a->bitmap, (u32)offs, (u32)blks);
 	alloc_dbg(na, "Free  0x%-10llx", addr);
 
 	a->bytes_freed += alloc->length;
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/pd_cache.c b/drivers/gpu/nvgpu/common/mm/gmmu/pd_cache.c
index 81b920bd2..bcde3d400 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu/pd_cache.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu/pd_cache.c
@@ -223,7 +223,7 @@ static int nvgpu_pd_cache_alloc_new(struct gk20a *g,
 	 * This allocates the very first PD table in the set of tables in this
 	 * nvgpu_pd_mem_entry.
 	 */
-	set_bit(0, pentry->alloc_map);
+	nvgpu_set_bit(0U, pentry->alloc_map);
 	pentry->allocs = 1;
 
 	/*
@@ -261,7 +261,7 @@ static int nvgpu_pd_cache_alloc_from_partial(struct gk20a *g,
 	/* Bit map full. Somethings wrong. */
 	nvgpu_assert(bit_offs < nr_bits);
 
-	set_bit((int)bit_offs, pentry->alloc_map);
+	nvgpu_set_bit((u32)bit_offs, pentry->alloc_map);
 	pentry->allocs += 1U;
 
 	/*
@@ -405,7 +405,7 @@ static void nvgpu_pd_cache_do_free(struct gk20a *g,
 	u32 bit = pd->mem_offs / pentry->pd_size;
 
 	/* Mark entry as free. */
-	clear_bit((int)bit, pentry->alloc_map);
+	nvgpu_clear_bit(bit, pentry->alloc_map);
 	pentry->allocs -= 1U;
 
 	if (pentry->allocs > 0U) {
diff --git a/drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c b/drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c
index cd44cde51..9b5d29ac8 100644
--- a/drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c
+++ b/drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c
@@ -126,7 +126,7 @@ int nvgpu_pmu_seq_acquire(struct gk20a *g,
 		return -EAGAIN;
 	}
 	nvgpu_assert(index <= U32_MAX);
-	set_bit((int)index, sequences->pmu_seq_tbl);
+	nvgpu_set_bit((u32)index, sequences->pmu_seq_tbl);
 	nvgpu_mutex_release(&sequences->pmu_seq_lock);
 
 	seq = &sequences->seq[index];
@@ -151,7 +151,7 @@ void nvgpu_pmu_seq_release(struct gk20a *g,
 	seq->out_payload = NULL;
 
 	nvgpu_mutex_acquire(&sequences->pmu_seq_lock);
-	clear_bit((int)seq->id, sequences->pmu_seq_tbl);
+	nvgpu_clear_bit(seq->id, sequences->pmu_seq_tbl);
 	nvgpu_mutex_release(&sequences->pmu_seq_lock);
 }
 
diff --git a/drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c b/drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c
index 72f875c28..8b425b385 100644
--- a/drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c
+++ b/drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c
@@ -87,7 +87,7 @@ int nvgpu_sec2_seq_acquire(struct gk20a *g,
 	}
 
 	nvgpu_assert(index < U64(INT_MAX));
-	set_bit(index, sequences->sec2_seq_tbl);
+	nvgpu_set_bit(index, sequences->sec2_seq_tbl);
 
 	nvgpu_mutex_release(&sequences->sec2_seq_lock);
 
@@ -113,7 +113,7 @@ static void sec2_seq_release(struct sec2_sequences *sequences,
 	seq->out_payload = NULL;
 
 	nvgpu_mutex_acquire(&sequences->sec2_seq_lock);
-	clear_bit(seq->id, sequences->sec2_seq_tbl);
+	nvgpu_clear_bit(seq->id, sequences->sec2_seq_tbl);
 	nvgpu_mutex_release(&sequences->sec2_seq_lock);
 }
 
diff --git a/drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c b/drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
index ac9c25cca..c84dd24b1 100644
--- a/drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
+++ b/drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
@@ -69,7 +69,7 @@ int nvgpu_hw_semaphore_init(struct nvgpu_channel *ch)
 	return 0;
 
 fail_free_idx:
-	clear_bit(hw_sema_idx, p->semas_alloced);
+	nvgpu_clear_bit((u32)hw_sema_idx, p->semas_alloced);
 fail:
 	nvgpu_mutex_release(&p->pool_lock);
 	return ret;
@@ -88,7 +88,7 @@ void nvgpu_hw_semaphore_free(struct nvgpu_channel *ch)
 
 	nvgpu_mutex_acquire(&p->pool_lock);
 
-	clear_bit(idx, p->semas_alloced);
+	nvgpu_clear_bit((u32)idx, p->semas_alloced);
 
 	nvgpu_kfree(ch->g, hw_sema);
 	ch->hw_sema = NULL;
diff --git a/drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c b/drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c
index c93fc1e11..1b0de85cb 100644
--- a/drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c
+++ b/drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c
@@ -213,7 +213,7 @@ static void nvgpu_semaphore_pool_free(struct nvgpu_ref *ref)
 
 	nvgpu_semaphore_sea_lock(s);
 	nvgpu_list_del(&p->pool_list_entry);
-	clear_bit((int)p->page_idx, s->pools_alloced);
+	nvgpu_clear_bit((u32)p->page_idx, s->pools_alloced);
 	s->page_count--;
 	nvgpu_semaphore_sea_unlock(s);
 
diff --git a/drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h b/drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h
index e630f681c..757c358b2 100644
--- a/drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h
+++ b/drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h
@@ -153,7 +153,7 @@ static inline int semaphore_bitmap_alloc(unsigned long *bitmap,
 		return -ENOSPC;
 	}
 
-	set_bit(idx, bitmap);
+	nvgpu_set_bit((u32)idx, bitmap);
 
 	return (int)idx;
 }
@@ -181,4 +181,4 @@ static inline bool nvgpu_semaphore_value_released(u32 goal, u32 racer)
 	return racer - goal < 0x80000000U;
 }
 
-#endif /* NVGPU_SEMAPHORE_PRIV_H */
\ No newline at end of file
+#endif /* NVGPU_SEMAPHORE_PRIV_H */
diff --git a/drivers/gpu/nvgpu/common/utils/enabled.c b/drivers/gpu/nvgpu/common/utils/enabled.c
index dc8c30a4f..5eeecd821 100644
--- a/drivers/gpu/nvgpu/common/utils/enabled.c
+++ b/drivers/gpu/nvgpu/common/utils/enabled.c
@@ -50,14 +50,14 @@ void nvgpu_free_enabled_flags(struct gk20a *g)
 
 bool nvgpu_is_enabled(struct gk20a *g, int flag)
 {
-	return test_bit(flag, g->enabled_flags);
+	return nvgpu_test_bit((u32)flag, g->enabled_flags);
 }
 
 void nvgpu_set_enabled(struct gk20a *g, int flag, bool state)
 {
 	if (state) {
-		set_bit(flag, g->enabled_flags);
+		nvgpu_set_bit((u32)flag, g->enabled_flags);
 	} else {
-		clear_bit(flag, g->enabled_flags);
+		nvgpu_clear_bit((u32)flag, g->enabled_flags);
 	}
 }
diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/runlist_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/runlist_vgpu.c
index f82aeb4d8..bdb035982 100644
--- a/drivers/gpu/nvgpu/common/vgpu/fifo/runlist_vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/fifo/runlist_vgpu.c
@@ -82,13 +82,13 @@ static bool vgpu_runlist_modify_active_locked(struct gk20a *g, u32 runlist_id,
 	runlist = f->runlist_info[runlist_id];
 
 	if (add) {
-		if (test_and_set_bit((int)ch->chid,
+		if (nvgpu_test_and_set_bit(ch->chid,
 				runlist->active_channels)) {
 			return false;
 			/* was already there */
 		}
 	} else {
-		if (!test_and_clear_bit((int)ch->chid,
+		if (!nvgpu_test_and_clear_bit(ch->chid,
 				runlist->active_channels)) {
 			/* wasn't there */
 			return false;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
index b1606cee1..a09216eed 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bitops.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
@@ -35,8 +35,7 @@
 #define BIT64(i)	(U64(1) << U64(i))
 
 #ifdef __KERNEL__
-#include <linux/bitops.h>
-#include <linux/bitmap.h>
+#include <nvgpu/linux/bitops.h>
 #else
 #include <nvgpu/posix/bitops.h>
 #endif
@@ -48,18 +47,4 @@
  */
 #define BITS_PER_BYTE_U32	8U
 
-static inline void nvgpu_bitmap_set(unsigned long *map, unsigned int start,
-				    unsigned int len)
-{
-	BUG_ON(len > U32(INT_MAX));
-	bitmap_set(map, start, (int)len);
-}
-
-static inline void nvgpu_bitmap_clear(unsigned long *map, unsigned int start,
-				      unsigned int len)
-{
-	BUG_ON(len > U32(INT_MAX));
-	bitmap_clear(map, start, (int)len);
-}
-
 #endif /* NVGPU_BITOPS_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/linux/bitops.h
new file mode 100644
index 000000000..704ab9ece
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/bitops.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef NVGPU_BITOPS_LINUX_H
+#define NVGPU_BITOPS_LINUX_H
+
+#include <linux/bitops.h>
+#include <linux/bitmap.h>
+
+static inline void nvgpu_bitmap_set(unsigned long *map, unsigned int start,
+					unsigned int len)
+{
+	BUG_ON(len > U32(INT_MAX));
+	bitmap_set(map, start, (int)len);
+}
+
+static inline void nvgpu_bitmap_clear(unsigned long *map, unsigned int start,
+					unsigned int len)
+{
+	BUG_ON(len > U32(INT_MAX));
+	bitmap_clear(map, start, (int)len);
+}
+
+static inline bool nvgpu_test_bit(unsigned int nr,
+					const volatile unsigned long *addr)
+{
+	BUG_ON(nr > U32(INT_MAX));
+	return test_bit((int)nr, addr);
+}
+
+static inline bool nvgpu_test_and_set_bit(unsigned int nr,
+						volatile unsigned long *addr)
+{
+	BUG_ON(nr > U32(INT_MAX));
+	return test_and_set_bit((int)nr, addr);
+}
+
+static inline bool nvgpu_test_and_clear_bit(unsigned int nr,
+						volatile unsigned long *addr)
+{
+	BUG_ON(nr > U32(INT_MAX));
+	return test_and_clear_bit((int)nr, addr);
+}
+
+static inline void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr)
+{
+	BUG_ON(nr > U32(INT_MAX));
+	set_bit((int)nr, addr);
+}
+
+static inline void nvgpu_clear_bit(unsigned int nr,
+					volatile unsigned long *addr)
+{
+	BUG_ON(nr > U32(INT_MAX));
+	clear_bit((int)nr, addr);
+}
+#endif /* NVGPU_LOCK_LINUX_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
index 4dc3e87cd..18b945929 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
@@ -64,18 +64,18 @@ unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
 unsigned long find_first_zero_bit(const unsigned long *addr,
 				  unsigned long size);
 
-bool test_bit(int nr, const volatile unsigned long *addr);
-bool test_and_set_bit(int nr, volatile unsigned long *addr);
-bool test_and_clear_bit(int nr, volatile unsigned long *addr);
+bool nvgpu_test_bit(unsigned int nr, const volatile unsigned long *addr);
+bool nvgpu_test_and_set_bit(unsigned int nr, volatile unsigned long *addr);
+bool nvgpu_test_and_clear_bit(unsigned int nr, volatile unsigned long *addr);
 
 /*
  * These two are atomic.
  */
-void set_bit(int nr, volatile unsigned long *addr);
-void clear_bit(int nr, volatile unsigned long *addr);
+void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr);
+void nvgpu_clear_bit(unsigned int nr, volatile unsigned long *addr);
 
-void bitmap_set(unsigned long *map, unsigned int start, int len);
-void bitmap_clear(unsigned long *map, unsigned int start, int len);
+void nvgpu_bitmap_set(unsigned long *map, unsigned int start, unsigned int len);
+void nvgpu_bitmap_clear(unsigned long *map, unsigned int start, unsigned int len);
 unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
 					     unsigned long size,
 					     unsigned long start,
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
index 7eb42dbab..393736fbc 100644
--- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
+++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
@@ -1,11 +1,8 @@
 # Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
 
-bitmap_clear
 bitmap_find_next_zero_area_off
-bitmap_set
 bug_handler_cancel
 bug_handler_register
-clear_bit
 gv11b_fb_read_mmu_fault_buffer_size
 gv11b_fb_read_mmu_fault_status
 gv11b_fb_write_mmu_fault_buffer_lo_hi
@@ -62,6 +59,8 @@ nvgpu_allocator_init
 nvgpu_aperture_mask
 nvgpu_bar1_readl
 nvgpu_bar1_writel
+nvgpu_bitmap_clear
+nvgpu_bitmap_set
 nvgpu_bsearch
 nvgpu_channel_alloc_inst
 nvgpu_channel_cleanup_sw
@@ -187,6 +186,7 @@ nvgpu_tsg_setup_sw
 nvgpu_tsg_unbind_channel
 nvgpu_tsg_unbind_channel_check_hw_state
 nvgpu_tsg_unbind_channel_check_ctx_reload
+nvgpu_set_bit
 nvgpu_set_enabled
 nvgpu_set_pte
 nvgpu_sgt_alignment
@@ -215,8 +215,8 @@ nvgpu_vm_unmap
 nvgpu_vzalloc_impl
 nvgpu_writel
 nvgpu_writel_check
-set_bit
-test_and_clear_bit
-test_and_set_bit
-test_bit
+nvgpu_clear_bit
+nvgpu_test_bit
+nvgpu_test_and_clear_bit
+nvgpu_test_and_set_bit
 vm_aspace_id
diff --git a/drivers/gpu/nvgpu/os/posix/bitmap.c b/drivers/gpu/nvgpu/os/posix/bitmap.c
index 4bf629dac..2a8e0cacf 100644
--- a/drivers/gpu/nvgpu/os/posix/bitmap.c
+++ b/drivers/gpu/nvgpu/os/posix/bitmap.c
@@ -33,7 +33,7 @@
 
 unsigned long nvgpu_posix_ffs(unsigned long word)
 {
-	return (unsigned long)__builtin_ffsl(word);
+	return (unsigned long)__builtin_ffsl((signed long)word);
 }
 
 unsigned long nvgpu_posix_fls(unsigned long word)
@@ -46,13 +46,14 @@ unsigned long nvgpu_posix_fls(unsigned long word)
 		 */
 		ret = 0UL;
 	} else {
-		ret = (sizeof(unsigned long) * 8UL) - __builtin_clzl(word);
+		ret = (sizeof(unsigned long) * 8UL) -
+			(unsigned long)__builtin_clzl(word);
 	}
 
 	return ret;
 }
 
-static unsigned long __find_next_bit(const unsigned long *addr,
+static unsigned long nvgpu_posix_find_next_bit(const unsigned long *addr,
 				     unsigned long n,
 				     unsigned long start,
 				     bool invert)
@@ -80,20 +81,20 @@ static unsigned long __find_next_bit(const unsigned long *addr,
 		return n;
 	}
 
-	start_mask = ~0UL << (start & (BITS_PER_LONG - 1));
+	start_mask = ~0UL << (start & (BITS_PER_LONG - 1UL));
 
 	idx = start / BITS_PER_LONG;
 	w = (addr[idx] ^ invert_mask) & start_mask;
 
 	start = round_up(start, BITS_PER_LONG);
 
-	idx_max = (n - 1) / BITS_PER_LONG;
+	idx_max = (n - 1UL) / BITS_PER_LONG;
 
 	/*
 	 * Find the first non-zero word taking into account start and
 	 * invert.
 	 */
-	while (!w) {
+	while (w == 0UL) {
 		idx++;
 		if (idx > idx_max) {
 			return n;
@@ -109,28 +110,28 @@ static unsigned long __find_next_bit(const unsigned long *addr,
 
 unsigned long find_first_bit(const unsigned long *addr, unsigned long size)
 {
-	return __find_next_bit(addr, size, 0, false);
+	return nvgpu_posix_find_next_bit(addr, size, 0, false);
 }
 
 unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size)
 {
-	return __find_next_bit(addr, size, 0, true);
+	return nvgpu_posix_find_next_bit(addr, size, 0, true);
 }
 
 unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
 			    unsigned long offset)
 {
-	return __find_next_bit(addr, size, offset, false);
+	return nvgpu_posix_find_next_bit(addr, size, offset, false);
 }
 
 static unsigned long find_next_zero_bit(const unsigned long *addr,
 					unsigned long size,
 					unsigned long offset)
 {
-	return __find_next_bit(addr, size, offset, true);
+	return nvgpu_posix_find_next_bit(addr, size, offset, true);
 }
 
-void bitmap_set(unsigned long *map, unsigned int start, int len)
+void nvgpu_bitmap_set(unsigned long *map, unsigned int start, unsigned int len)
 {
 	unsigned int end = start + len;
 
@@ -138,16 +139,16 @@ void bitmap_set(unsigned long *map, unsigned int start, int len)
 	 * Super slow naive implementation. But speed isn't what matters here.
 	 */
 	while (start < end) {
-		set_bit(start++, map);
+		nvgpu_set_bit(start++, map);
 	}
 }
 
-void bitmap_clear(unsigned long *map, unsigned int start, int len)
+void nvgpu_bitmap_clear(unsigned long *map, unsigned int start, unsigned int len)
 {
 	unsigned int end = start + len;
 
 	while (start < end) {
-		clear_bit(start++, map);
+		nvgpu_clear_bit(start++, map);
 	}
 }
 
@@ -185,7 +186,7 @@ unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
 			return start;
 		}
 
-		start = offs + 1;
+		start = offs + 1UL;
 	}
 
 	return size;
@@ -201,12 +202,13 @@ unsigned long bitmap_find_next_zero_area(unsigned long *map,
 					      align_mask, 0);
 }
 
-bool test_bit(int nr, const volatile unsigned long *addr)
+bool nvgpu_test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
-	return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+	return (1UL & (addr[BIT_WORD(nr)] >>
+			(nr & (BITS_PER_LONG-1UL)))) != 0UL;
 }
 
-bool test_and_set_bit(int nr, volatile unsigned long *addr)
+bool nvgpu_test_and_set_bit(unsigned int nr, volatile unsigned long *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
 	volatile unsigned long *p = addr + BIT_WORD(nr);
@@ -214,27 +216,26 @@ bool test_and_set_bit(int nr, volatile unsigned long *addr)
 	return (atomic_fetch_or(p, mask) & mask) != 0ULL;
 }
 
-bool test_and_clear_bit(int nr, volatile unsigned long *addr)
+bool nvgpu_test_and_clear_bit(unsigned int nr, volatile unsigned long *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
-	volatile unsigned long *p =
-		((volatile unsigned long *)addr) + BIT_WORD(nr);
+	volatile unsigned long *p = addr + BIT_WORD(nr);
 
 	return (atomic_fetch_and(p, ~mask) & mask) != 0ULL;
 }
 
-void set_bit(int nr, volatile unsigned long *addr)
+void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	volatile unsigned long *p = addr + BIT_WORD(nr);
 
 	(void)atomic_fetch_or(p, mask);
 }
 
-void clear_bit(int nr, volatile unsigned long *addr)
+void nvgpu_clear_bit(unsigned int nr, volatile unsigned long *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	volatile unsigned long *p = addr + BIT_WORD(nr);
 
 	(void)atomic_fetch_and(p, ~mask);
 }
diff --git a/userspace/units/fifo/tsg/nvgpu-tsg.c b/userspace/units/fifo/tsg/nvgpu-tsg.c
index 843a1f7d3..cc117e9b5 100644
--- a/userspace/units/fifo/tsg/nvgpu-tsg.c
+++ b/userspace/units/fifo/tsg/nvgpu-tsg.c
@@ -327,9 +327,9 @@ static int test_tsg_bind_channel(struct unit_module *m,
 		/* ch already already active */
 		runlist = &f->active_runlist_info[tsg->runlist_id];
 		if (branches & F_TSG_BIND_CHANNEL_ACTIVE) {
-			set_bit((int)ch->chid, runlist->active_channels);
+			nvgpu_set_bit(ch->chid, runlist->active_channels);
 		} else {
-			clear_bit((int)ch->chid, runlist->active_channels);
+			nvgpu_clear_bit(ch->chid, runlist->active_channels);
 		}
 
 		g->ops.tsg.bind_channel =
diff --git a/userspace/units/posix/bitops/posix-bitops.c b/userspace/units/posix/bitops/posix-bitops.c
index 03565aabe..867821c31 100644
--- a/userspace/units/posix/bitops/posix-bitops.c
+++ b/userspace/units/posix/bitops/posix-bitops.c
@@ -509,7 +509,7 @@ static int test_single_bitops(struct unit_module *m,
 	 * First set all the bits and make sure the words are set.
 	 */
 	for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
-		set_bit(i, words);
+		nvgpu_set_bit(i, words);
 
 	if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG,
 			    0, NUM_WORDS * BITS_PER_LONG, false)) {
@@ -521,11 +521,11 @@ static int test_single_bitops(struct unit_module *m,
 	 * Now make sure the test_bit works for set bits.
 	 */
 	for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
-		if (!test_bit(i, words))
+		if (!nvgpu_test_bit(i, words))
 			unit_return_fail(m, "test_bit: bit %d failed!\n", i);
 
 	for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
-		clear_bit(i, words);
+		nvgpu_clear_bit(i, words);
 
 	if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG,
 			    0, NUM_WORDS * BITS_PER_LONG, true)) {
@@ -534,7 +534,7 @@ static int test_single_bitops(struct unit_module *m,
 	}
 
 	for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
-		if (test_bit(i, words))
+		if (nvgpu_test_bit(i, words))
 			unit_return_fail(m, "test_bit: bit %d failed!\n", i);
 
 	return UNIT_SUCCESS;
@@ -544,8 +544,8 @@ static int test_bit_setclear(struct unit_module *m,
 			     struct gk20a *g, void *__args)
 {
 	struct test_setclear_args *args = __args;
-	void (*testfn)(int, volatile unsigned long *) =
-		args->clear ? clear_bit : set_bit;
+	void (*testfn)(unsigned int, volatile unsigned long *) =
+		args->clear ? nvgpu_clear_bit : nvgpu_set_bit;
 	unsigned long words[NUM_WORDS];
 	unsigned int i;
 
@@ -569,10 +569,10 @@ static int test_test_and_setclear_bit(struct unit_module *m,
 				      struct gk20a *g, void *__args)
 {
 	struct test_setclear_args *args = __args;
-	bool (*testfn)(int, volatile unsigned long *) =
-		args->clear ? test_and_clear_bit : test_and_set_bit;
-	bool (*testfn_reset)(int, volatile unsigned long *) =
-		args->clear ? test_and_set_bit : test_and_clear_bit;
+	bool (*testfn)(unsigned int, volatile unsigned long *) =
+		args->clear ? nvgpu_test_and_clear_bit : nvgpu_test_and_set_bit;
+	bool (*testfn_reset)(unsigned int, volatile unsigned long *) =
+		args->clear ? nvgpu_test_and_set_bit : nvgpu_test_and_clear_bit;
 	unsigned long words[NUM_WORDS];
 	unsigned int i;
 
@@ -618,8 +618,8 @@ static int test_bitmap_setclear(struct unit_module *m,
 				struct gk20a *g, void *__args)
 {
 	struct test_setclear_args *args = __args;
-	void (*testfn)(unsigned long *, unsigned int, int) =
-		args->clear ? bitmap_clear : bitmap_set;
+	void (*testfn)(unsigned long *, unsigned int, unsigned int) =
+		args->clear ? nvgpu_bitmap_clear : nvgpu_bitmap_set;
 	unsigned long words[NUM_WORDS];
 	unsigned long i, j;
 	int set_char = args->clear ? 0xff : 0x0;