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gpu: nvgpu: pmc access through pmc driver

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The pmc access has to be through pmc driver. This prevents the direct access
to pmc registers and supports onlt tz access to it in t210 platforms.

Bug 1811649

Change-Id: I235768a07fa93ce4cced656aade160bbd853be62
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704315
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
kalyani chidambaram
2018-04-27 16:47:37 -07:00
committed by mobile promotions
parent e540bf87ae
commit a7288b5867
1 changed files with 5 additions and 16 deletions
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21
drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
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@@ -55,6 +55,7 @@
#include "os_linux.h"
#include "../../../arch/arm/mach-tegra/iomap.h"
#include <soc/tegra/pmc.h>
#define TEGRA_GK20A_BW_PER_FREQ 32
#define TEGRA_GM20B_BW_PER_FREQ 64
@@ -84,16 +85,6 @@ struct gk20a_emc_params {
};
#endif
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
static inline u32 __maybe_unused pmc_read(unsigned long reg)
{
return readl(pmc + reg);
}
static inline void __maybe_unused pmc_write(u32 val, unsigned long reg)
{
writel_relaxed(val, pmc + reg);
}
#define MHZ_TO_HZ(x) ((x) * 1000000)
#define HZ_TO_MHZ(x) ((x) / 1000000)
@@ -326,8 +317,8 @@ static int gm20b_tegra_railgate(struct device *dev)
udelay(10);
/* enable clamp */
pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
pmc_read(PMC_GPU_RG_CNTRL_0);
tegra_pmc_writel_relaxed(0x1, PMC_GPU_RG_CNTRL_0);
tegra_pmc_readl(PMC_GPU_RG_CNTRL_0);
udelay(10);
@@ -435,8 +426,8 @@ static int gm20b_tegra_unrailgate(struct device *dev)
udelay(10);
pmc_write(0, PMC_GPU_RG_CNTRL_0);
pmc_read(PMC_GPU_RG_CNTRL_0);
tegra_pmc_writel_relaxed(0, PMC_GPU_RG_CNTRL_0);
tegra_pmc_readl(PMC_GPU_RG_CNTRL_0);
udelay(10);
@@ -833,8 +824,6 @@ static int gk20a_tegra_probe(struct device *dev)
return ret;
}
pmc = ioremap(TEGRA_PMC_BASE, 4096);
return 0;
}