diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index e077ea429..0aab62696 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -33,6 +33,7 @@ ccflags-y += -DNVGPU_REPLAYABLE_FAULT ccflags-y += -DNVGPU_GRAPHICS ccflags-y += -DNVGPU_FEATURE_CHANNEL_TSG_SCHEDULING ccflags-y += -DNVGPU_FEATURE_CHANNEL_TSG_CONTROL +ccflags-y += -DNVGPU_FEATURE_POWER_PG ccflags-y += -DNVGPU_FEATURE_CE obj-$(CONFIG_GK20A) := nvgpu.o diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index 399c32c45..308ebdd61 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -122,4 +122,8 @@ NVGPU_COMMON_CFLAGS += -DNVGPU_REPLAYABLE_FAULT # Enable LS PMU support for normal build NVGPU_FEATURE_LS_PMU := 1 NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_LS_PMU + +# Enable elpg support for normal build +NVGPU_FEATURE_POWER_PG := 1 +NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_POWER_PG endif diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 93def828e..9c303a28d 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -128,7 +128,6 @@ srcs += common/utils/enabled.c \ common/semaphore/semaphore.c \ common/power_features/power_features.c \ common/power_features/cg/cg.c \ - common/power_features/pg/pg.c \ common/fifo/preempt.c \ common/fifo/channel.c \ common/rc/rc.c \ @@ -419,6 +418,10 @@ srcs += \ hal/pmu/pmu_tu104.c endif +ifeq ($(NVGPU_FEATURE_POWER_PG), 1) +srcs += common/power_features/pg/pg.c +endif + ifeq ($(IGPU_VIRT_SUPPORT), 1) srcs += common/vgpu/init/init_vgpu.c \ common/vgpu/init/init_hal_vgpu.c \ diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 5defafede..a23a8dc32 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -534,9 +534,11 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) } if (engine_enum == NVGPU_ENGINE_GR) { +#ifdef NVGPU_FEATURE_POWER_PG if (nvgpu_pg_elpg_disable(g) != 0 ) { nvgpu_err(g, "failed to set disable elpg"); } +#endif #ifdef CONFIG_GK20A_CTXSW_TRACE /* @@ -575,9 +577,11 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) "gr cannot be reset without halting gr pipe"); } +#ifdef NVGPU_FEATURE_POWER_PG if (nvgpu_pg_elpg_enable(g) != 0 ) { nvgpu_err(g, "failed to set enable elpg"); } +#endif } if ((engine_enum == NVGPU_ENGINE_GRCE) || diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 41a55b213..085cc9886 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -732,13 +732,16 @@ int nvgpu_gr_disable_ctxsw(struct gk20a *g) gr->ctxsw_disable_count++; if (gr->ctxsw_disable_count == 1) { +#ifdef NVGPU_FEATURE_POWER_PG err = nvgpu_pg_elpg_disable(g); if (err != 0) { nvgpu_err(g, "failed to disable elpg for stop_ctxsw"); /* stop ctxsw command is not sent */ gr->ctxsw_disable_count--; - } else { + } else +#endif + { err = g->ops.gr.falcon.ctrl_ctxsw(g, NVGPU_GR_FALCON_METHOD_CTXSW_STOP, 0U, NULL); if (err != 0) { @@ -775,12 +778,15 @@ int nvgpu_gr_enable_ctxsw(struct gk20a *g) NVGPU_GR_FALCON_METHOD_CTXSW_START, 0U, NULL); if (err != 0) { nvgpu_err(g, "failed to start fecs ctxsw"); - } else { + } +#ifdef NVGPU_FEATURE_POWER_PG + else { if (nvgpu_pg_elpg_enable(g) != 0) { nvgpu_err(g, "failed to enable elpg for start_ctxsw"); } } +#endif } else { nvgpu_log_info(g, "ctxsw_disable_count: %d is not 0 yet", gr->ctxsw_disable_count); diff --git a/drivers/gpu/nvgpu/common/power_features/power_features.c b/drivers/gpu/nvgpu/common/power_features/power_features.c index a357b401b..fc849ee5e 100644 --- a/drivers/gpu/nvgpu/common/power_features/power_features.c +++ b/drivers/gpu/nvgpu/common/power_features/power_features.c @@ -33,11 +33,13 @@ int nvgpu_cg_pg_disable(struct gk20a *g) g->ops.gr.init.wait_initialized(g); +#ifdef NVGPU_FEATURE_POWER_PG /* disable elpg before clock gating */ err = nvgpu_pg_elpg_disable(g); if (err != 0) { nvgpu_err(g, "failed to set disable elpg"); } +#endif nvgpu_cg_slcg_gr_perf_ltc_load_disable(g); nvgpu_cg_blcg_mode_disable(g); @@ -61,10 +63,12 @@ int nvgpu_cg_pg_enable(struct gk20a *g) nvgpu_cg_slcg_gr_perf_ltc_load_enable(g); +#ifdef NVGPU_FEATURE_POWER_PG err = nvgpu_pg_elpg_enable(g); if (err != 0) { nvgpu_err(g, "failed to set enable elpg"); } +#endif return err; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h index 7518949da..388ae5399 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h @@ -28,6 +28,7 @@ struct gk20a; +#ifdef NVGPU_FEATURE_POWER_PG #define nvgpu_pg_elpg_protected_call(g, func) \ ({ \ int err = 0; \ @@ -41,6 +42,9 @@ struct gk20a; } \ err; \ }) +#else +#define nvgpu_pg_elpg_protected_call(g, func) func +#endif int nvgpu_pg_elpg_disable(struct gk20a *g); int nvgpu_pg_elpg_enable(struct gk20a *g);