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gpu: nvgpu: mm: fix MISRA 10.3 issues in nvgpu_mem
MISRA Rule 10.3 prohibits implicit assignment of an object of different essential type or narrower type. This change addresses a number of miscellaneous violations in nvgpu_mem.c. Change-Id: Id4bb0105fe649bc19735dafec53a1aac1044f7fa Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1998088 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,7 +53,7 @@ u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture,
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case APERTURE_VIDMEM:
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return vidmem_mask;
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case APERTURE_INVALID:
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WARN_ON("Bad aperture");
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(void)WARN(true, "Bad aperture");
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}
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return 0;
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}
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@@ -111,9 +111,10 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
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WARN_ON(ptr == NULL);
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data = ptr[w];
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} else if (mem->aperture == APERTURE_VIDMEM) {
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nvgpu_pramin_rd_n(g, mem, w * sizeof(u32), sizeof(u32), &data);
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nvgpu_pramin_rd_n(g, mem, w * (u32)sizeof(u32),
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(u32)sizeof(u32), &data);
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} else {
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WARN_ON("Accessing unallocated nvgpu_mem");
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(void)WARN(true, "Accessing unallocated nvgpu_mem");
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}
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return data;
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@@ -130,7 +131,7 @@ u64 nvgpu_mem_rd32_pair(struct gk20a *g, struct nvgpu_mem *mem, u32 lo, u32 hi)
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u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
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{
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WARN_ON((offset & 3U) != 0U);
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return nvgpu_mem_rd32(g, mem, offset / sizeof(u32));
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return nvgpu_mem_rd32(g, mem, offset / (u32)sizeof(u32));
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}
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void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
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@@ -147,7 +148,7 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
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} else if (mem->aperture == APERTURE_VIDMEM) {
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nvgpu_pramin_rd_n(g, mem, offset, size, dest);
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} else {
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WARN_ON("Accessing unallocated nvgpu_mem");
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(void)WARN(true, "Accessing unallocated nvgpu_mem");
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}
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}
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@@ -159,19 +160,20 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
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WARN_ON(ptr == NULL);
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ptr[w] = data;
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} else if (mem->aperture == APERTURE_VIDMEM) {
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nvgpu_pramin_wr_n(g, mem, w * sizeof(u32), sizeof(u32), &data);
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nvgpu_pramin_wr_n(g, mem, w * (u32)sizeof(u32),
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(u32)sizeof(u32), &data);
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if (!mem->skip_wmb) {
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nvgpu_wmb();
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}
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} else {
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WARN_ON("Accessing unallocated nvgpu_mem");
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(void)WARN(true, "Accessing unallocated nvgpu_mem");
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}
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}
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void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
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{
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WARN_ON((offset & 3U) != 0U);
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nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data);
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nvgpu_mem_wr32(g, mem, offset / (u32)sizeof(u32), data);
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}
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void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
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@@ -191,7 +193,7 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
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nvgpu_wmb();
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}
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} else {
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WARN_ON("Accessing unallocated nvgpu_mem");
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(void)WARN(true, "Accessing unallocated nvgpu_mem");
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}
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}
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@@ -208,7 +210,7 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
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u8 *dest = (u8 *)mem->cpu_va + offset;
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WARN_ON(mem->cpu_va == NULL);
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(void) memset(dest, c, size);
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(void) memset(dest, (int)c, size);
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} else if (mem->aperture == APERTURE_VIDMEM) {
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u32 repeat_value = c | (c << 8) | (c << 16) | (c << 24);
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@@ -217,6 +219,6 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
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nvgpu_wmb();
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}
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} else {
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WARN_ON("Accessing unallocated nvgpu_mem");
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(void)WARN(true, "Accessing unallocated nvgpu_mem");
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}
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}
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