diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
index a8d4fdb70..88178c28c 100644
--- a/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,7 @@
 #include <nvgpu/regops_allowlist.h>
 #include "allowlist_ga100.h"
 
-u32 ga100_hwpm_perfmon_register_offset_allowlist[] = {
+static const u32 ga100_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000004,
 	0x00000008,
@@ -93,7 +93,7 @@ u32 ga100_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000130,
 };
 
-u32 ga100_hwpm_router_register_offset_allowlist[] = {
+static const u32 ga100_hwpm_router_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000008,
 	0x00000010,
@@ -101,7 +101,7 @@ u32 ga100_hwpm_router_register_offset_allowlist[] = {
 	0x00000150,
 };
 
-u32 ga100_hwpm_pma_channel_register_offset_allowlist[] = {
+static const u32 ga100_hwpm_pma_channel_register_offset_allowlist[] = {
 	0x0000000c,
 	0x00000610,
 	0x00000618,
@@ -113,7 +113,7 @@ u32 ga100_hwpm_pma_channel_register_offset_allowlist[] = {
 	0x0000075c,
 };
 
-u32 ga100_hwpm_pma_trigger_register_offset_allowlist[] = {
+static const u32 ga100_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x00000008,
 	0x00000600,
 	0x00000604,
@@ -176,7 +176,7 @@ u32 ga100_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x0000075c,
 };
 
-u32 ga100_smpc_register_offset_allowlist[] = {
+static const u32 ga100_smpc_register_offset_allowlist[] = {
 	0x00000200,
 	0x00000204,
 	0x00000208,
@@ -348,7 +348,7 @@ u32 ga100_smpc_register_offset_allowlist[] = {
 	0x000007c4,
 };
 
-u32 ga100_cau_register_offset_allowlist[] = {
+static const u32 ga100_cau_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000004,
 	0x00000008,
@@ -360,7 +360,7 @@ u32 ga100_cau_register_offset_allowlist[] = {
 	0x00000024,
 };
 
-const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmon_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmon_register_ranges[] = {
 	{0x00180000, 0x0019fffc},
 	{0x00250040, 0x00250124},
 	{0x00250240, 0x00250324},
@@ -369,7 +369,7 @@ const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmon_register_ranges
 	{0x00260000, 0x00267ffc},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_hwpm_router_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_hwpm_router_register_ranges[] = {
 	{0x00244000, 0x00244ffc},
 	{0x00246000, 0x002477fc},
 	{0x00248000, 0x002481fc},
@@ -379,26 +379,26 @@ const struct nvgpu_pm_resource_register_range ga100_hwpm_router_register_ranges[
 	{0x00251b50, 0x00251b50},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_channel_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_channel_register_ranges[] = {
 	{0x0024a610, 0x0024a628},
 	{0x0024a634, 0x0024a658},
 	{0x0024a730, 0x0024a734},
 	{0x0024a00c, 0x0024a00c},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_trigger_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_trigger_register_ranges[] = {
 	{0x0024a000, 0x0024a008},
 	{0x0024a010, 0x0024a60c},
 	{0x0024a62c, 0x0024a62c},
 	{0x0024a65c, 0x0024a72c},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_smpc_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_smpc_register_ranges[] = {
 	{0x00580000, 0x005bfffc},
 	{0x00480000, 0x004bfffc},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register_ranges[] = {
 	{0x00140028, 0x00140028},
 	{0x00142028, 0x00142028},
 	{0x00144028, 0x00144028},
@@ -1427,7 +1427,7 @@ const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register_ranges
 	{0x0013cb94, 0x0013cb94},
 };
 
-const struct nvgpu_pm_resource_register_range ga100_cau_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga100_cau_register_ranges[] = {
 	{0x00504180, 0x005041b4},
 	{0x005041c0, 0x005041f4},
 	{0x00504980, 0x005049b4},
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
index 7249a05e9..fb73bd74d 100644
--- a/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
@@ -26,7 +26,7 @@
 #include <nvgpu/regops_allowlist.h>
 #include "allowlist_ga10b.h"
 
-u32 ga10b_hwpm_perfmon_register_offset_allowlist[] = {
+static const u32 ga10b_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000004,
 	0x00000008,
@@ -91,7 +91,7 @@ u32 ga10b_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000130,
 };
 
-u32 ga10b_hwpm_router_register_offset_allowlist[] = {
+static const u32 ga10b_hwpm_router_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000008,
 	0x00000010,
@@ -99,7 +99,7 @@ u32 ga10b_hwpm_router_register_offset_allowlist[] = {
 	0x00000150,
 };
 
-u32 ga10b_hwpm_pma_channel_register_offset_allowlist[] = {
+static const u32 ga10b_hwpm_pma_channel_register_offset_allowlist[] = {
 	0x0000000c,
 	0x00000610,
 	0x00000618,
@@ -111,7 +111,7 @@ u32 ga10b_hwpm_pma_channel_register_offset_allowlist[] = {
 	0x0000075c,
 };
 
-u32 ga10b_hwpm_pma_trigger_register_offset_allowlist[] = {
+static const u32 ga10b_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x00000008,
 	0x00000600,
 	0x00000604,
@@ -174,7 +174,7 @@ u32 ga10b_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x0000075c,
 };
 
-u32 ga10b_smpc_register_offset_allowlist[] = {
+static const u32 ga10b_smpc_register_offset_allowlist[] = {
 	0x00000200,
 	0x00000204,
 	0x00000208,
@@ -346,7 +346,7 @@ u32 ga10b_smpc_register_offset_allowlist[] = {
 	0x000007c4,
 };
 
-u32 ga10b_cau_register_offset_allowlist[] = {
+static const u32 ga10b_cau_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000004,
 	0x00000008,
@@ -358,7 +358,7 @@ u32 ga10b_cau_register_offset_allowlist[] = {
 	0x00000024,
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmon_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmon_register_ranges[] = {
 	{0x00180000, 0x00187ffc},
 	{0x00250040, 0x00250124},
 	{0x00250240, 0x00250324},
@@ -367,7 +367,7 @@ const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmon_register_ranges
 	{0x00260000, 0x00263ffc},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_hwpm_router_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_hwpm_router_register_ranges[] = {
 	{0x00244000, 0x002443fc},
 	{0x00246000, 0x002463fc},
 	{0x00248000, 0x002481fc},
@@ -377,7 +377,7 @@ const struct nvgpu_pm_resource_register_range ga10b_hwpm_router_register_ranges[
 	{0x00251b50, 0x00251b50},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_channel_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_channel_register_ranges[] = {
 	{0x0024a00c, 0x0024a00c},
 	{0x0024a610, 0x0024a628},
 	{0x0024a634, 0x0024a658},
@@ -385,19 +385,19 @@ const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_channel_register_ra
 	{0x0024a75c, 0x0024a75c},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_trigger_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_trigger_register_ranges[] = {
 	{0x0024a000, 0x0024a008},
 	{0x0024a6d0, 0x0024a60c},
 	{0x0024a62c, 0x0024a62c},
 	{0x0024a65c, 0x0024a72c},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_smpc_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_smpc_register_ranges[] = {
 	{0x00580000, 0x0058fffc},
 	{0x00480000, 0x0048fffc},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmux_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmux_register_ranges[] = {
 	{0x00140028, 0x00140028},
 	{0x00142028, 0x00142028},
 	{0x0017e028, 0x0017e028},
@@ -652,7 +652,7 @@ const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmux_register_ranges
 	{0x0013cb94, 0x0013cb94},
 };
 
-const struct nvgpu_pm_resource_register_range ga10b_cau_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range ga10b_cau_register_ranges[] = {
 	{0x00504180, 0x005041ac},
 	{0x005041b4, 0x005041e8},
 	{0x005041f4, 0x005041fc},
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.c b/drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.c
index 16375cc9c..43460c32c 100644
--- a/drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,7 @@
 #include <nvgpu/regops_allowlist.h>
 #include "allowlist_gv11b.h"
 
-u32 gv11b_hwpm_perfmon_register_offset_allowlist[] = {
+static const u32 gv11b_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000040,
 	0x00000044,
 	0x00000048,
@@ -80,19 +80,19 @@ u32 gv11b_hwpm_perfmon_register_offset_allowlist[] = {
 	0x00000124,
 };
 
-u32 gv11b_hwpm_router_register_offset_allowlist[] = {
+static const u32 gv11b_hwpm_router_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000008,
 	0x00000010,
 	0x00000014,
 };
 
-u32 gv11b_hwpm_pma_channel_register_offset_allowlist[] = {
+static const u32 gv11b_hwpm_pma_channel_register_offset_allowlist[] = {
 	0x00000080,
 	0x00000084,
 };
 
-u32 gv11b_hwpm_pma_trigger_register_offset_allowlist[] = {
+static const u32 gv11b_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x00000000,
 	0x00000008,
 	0x00000010,
@@ -131,7 +131,7 @@ u32 gv11b_hwpm_pma_trigger_register_offset_allowlist[] = {
 	0x00000608,
 };
 
-u32 gv11b_smpc_register_offset_allowlist[] = {
+static const u32 gv11b_smpc_register_offset_allowlist[] = {
 	0x00000200,
 	0x00000204,
 	0x00000208,
@@ -303,7 +303,7 @@ u32 gv11b_smpc_register_offset_allowlist[] = {
 	0x000007c4,
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmon_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmon_register_ranges[] = {
 	{0x00180000, 0x00183ffc},
 	{0x00250040, 0x00250124},
 	{0x00250240, 0x00250324},
@@ -315,7 +315,7 @@ const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmon_register_ranges
 	{0x00240000, 0x00243ffc},
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_hwpm_router_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_hwpm_router_register_ranges[] = {
 	{0x00244000, 0x002441fc},
 	{0x00246000, 0x002461fc},
 	{0x00248000, 0x002481fc},
@@ -323,21 +323,21 @@ const struct nvgpu_pm_resource_register_range gv11b_hwpm_router_register_ranges[
 	{0x00251a00, 0x00251a14},
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_hwpm_pma_channel_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_hwpm_pma_channel_register_ranges[] = {
 	{0x0024a070, 0x0024a08c},
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_hwpm_pma_trigger_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_hwpm_pma_trigger_register_ranges[] = {
 	{0x0024a000, 0x0024a06c},
 	{0x0024a090, 0x0024bffb},
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_smpc_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_smpc_register_ranges[] = {
 	{0x00580000, 0x00587ffc},
 	{0x00480000, 0x00487ffc},
 };
 
-const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmux_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmux_register_ranges[] = {
 	{0x000004f0, 0x000004f0},
 	{0x00001a00, 0x00001a00},
 	{0x000884e0, 0x000884e0},
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_tu104.c b/drivers/gpu/nvgpu/hal/regops/allowlist_tu104.c
index b7353c57b..3bcd0566a 100644
--- a/drivers/gpu/nvgpu/hal/regops/allowlist_tu104.c
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_tu104.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -327,7 +327,7 @@ static const u32 tu104_cau_register_offset_allowlist[] = {
 	0x00000024,
 };
 
-const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmon_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmon_register_ranges[] = {
 	{0x00180000, 0x00197ffc},
 	{0x00250040, 0x00250124},
 	{0x00250240, 0x00250324},
@@ -341,7 +341,7 @@ const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmon_register_ranges
 	{0x00251240, 0x00251324},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_hwpm_router_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_hwpm_router_register_ranges[] = {
 	{0x00244000, 0x00244bfc},
 	{0x00246000, 0x00246ffc},
 	{0x00248000, 0x002481fc},
@@ -349,21 +349,21 @@ const struct nvgpu_pm_resource_register_range tu104_hwpm_router_register_ranges[
 	{0x00251a00, 0x00251a14},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_hwpm_pma_channel_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_hwpm_pma_channel_register_ranges[] = {
 	{0x0024a070, 0x0024a08c},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_hwpm_pma_trigger_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_hwpm_pma_trigger_register_ranges[] = {
 	{0x0024a000, 0x0024a06c},
 	{0x0024a090, 0x0024bffb},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_smpc_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_smpc_register_ranges[] = {
 	{0x00580000, 0x005afffc},
 	{0x00480000, 0x004afffc},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmux_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmux_register_ranges[] = {
 	{0x000004f0, 0x000004f0},
 	{0x000010c0, 0x000010c0},
 	{0x00001a00, 0x00001a00},
@@ -1117,7 +1117,7 @@ const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmux_register_ranges
 	{0x00a1ec70, 0x00a1ec74},
 };
 
-const struct nvgpu_pm_resource_register_range tu104_cau_register_ranges[] = {
+static const struct nvgpu_pm_resource_register_range tu104_cau_register_ranges[] = {
 	{0x00419980, 0x004199b4},
 	{0x004199c0, 0x004199f4},
 	{0x0041c180, 0x0041c1b4},