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gpu: nvgpu: vgpu: explicitly set values for big enums

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It helps when a few people add ivc cmds at same time.
It can also decouple the changes when integrating to other branches.

JIRA VFND-1903

Change-Id: I1d9b6cc0443b230dd7da4a0c1b445af2acb0487c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1162741
(cherry picked from commit b40c06fd0ec92cba932497892a9242b702b5d3d7)
Reviewed-on: http://git-master/r/1167286
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2016-06-09 16:43:37 -07:00
committed by Terje Bergstrom
parent cfb067b6d7
commit a79135eacb
1 changed files with 104 additions and 104 deletions
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208
include/linux/tegra_vgpu.h
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@@ -37,65 +37,65 @@ enum {
enum {
TEGRA_VGPU_CMD_CONNECT = 0,
TEGRA_VGPU_CMD_DISCONNECT,
TEGRA_VGPU_CMD_ABORT,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX,
TEGRA_VGPU_CMD_GET_ATTRIBUTE,
TEGRA_VGPU_CMD_MAP_BAR1,
TEGRA_VGPU_CMD_AS_ALLOC_SHARE,
TEGRA_VGPU_CMD_AS_BIND_SHARE,
TEGRA_VGPU_CMD_AS_FREE_SHARE,
TEGRA_VGPU_CMD_AS_MAP,
TEGRA_VGPU_CMD_AS_UNMAP,
TEGRA_VGPU_CMD_AS_INVALIDATE,
TEGRA_VGPU_CMD_CHANNEL_BIND,
TEGRA_VGPU_CMD_CHANNEL_UNBIND,
TEGRA_VGPU_CMD_CHANNEL_DISABLE,
TEGRA_VGPU_CMD_CHANNEL_PREEMPT,
TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX, /* deprecated */
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX, /* deprecated */
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX,
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX,
TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX,
TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL,
TEGRA_VGPU_CMD_CACHE_MAINT,
TEGRA_VGPU_CMD_SUBMIT_RUNLIST,
TEGRA_VGPU_CMD_GET_ZCULL_INFO,
TEGRA_VGPU_CMD_ZBC_SET_TABLE,
TEGRA_VGPU_CMD_ZBC_QUERY_TABLE,
TEGRA_VGPU_CMD_AS_MAP_EX,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
TEGRA_VGPU_CMD_REG_OPS,
TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE,
TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE,
TEGRA_VGPU_CMD_FECS_TRACE_ENABLE,
TEGRA_VGPU_CMD_FECS_TRACE_DISABLE,
TEGRA_VGPU_CMD_FECS_TRACE_POLL,
TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER,
TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE,
TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX,
TEGRA_VGPU_CMD_GR_CTX_ALLOC,
TEGRA_VGPU_CMD_GR_CTX_FREE,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX,
TEGRA_VGPU_CMD_TSG_BIND_GR_CTX,
TEGRA_VGPU_CMD_TSG_BIND_CHANNEL,
TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL,
TEGRA_VGPU_CMD_TSG_PREEMPT,
TEGRA_VGPU_CMD_TSG_SET_TIMESLICE,
TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE,
TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET,
TEGRA_VGPU_CMD_CHANNEL_ENABLE,
TEGRA_VGPU_CMD_READ_PTIMER,
TEGRA_VGPU_CMD_DISCONNECT = 1,
TEGRA_VGPU_CMD_ABORT = 2,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4,
TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5,
TEGRA_VGPU_CMD_MAP_BAR1 = 6,
TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7,
TEGRA_VGPU_CMD_AS_BIND_SHARE = 8,
TEGRA_VGPU_CMD_AS_FREE_SHARE = 9,
TEGRA_VGPU_CMD_AS_MAP = 10,
TEGRA_VGPU_CMD_AS_UNMAP = 11,
TEGRA_VGPU_CMD_AS_INVALIDATE = 12,
TEGRA_VGPU_CMD_CHANNEL_BIND = 13,
TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14,
TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15,
TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16,
TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX = 18, /* deprecated */
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX = 19, /* deprecated */
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21,
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22,
TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23,
TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25,
TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26,
TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27,
TEGRA_VGPU_CMD_CACHE_MAINT = 28,
TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29,
TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30,
TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31,
TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32,
TEGRA_VGPU_CMD_AS_MAP_EX = 33,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34,
TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35,
TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36,
TEGRA_VGPU_CMD_REG_OPS = 37,
TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38,
TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39,
TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40,
TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41,
TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42,
TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43,
TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44,
TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45,
TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX =50,
TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51,
TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,
TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53,
TEGRA_VGPU_CMD_TSG_PREEMPT = 54,
TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55,
TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56,
TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57,
TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
TEGRA_VGPU_CMD_READ_PTIMER = 59,
};
struct tegra_vgpu_connect_params {
@@ -111,27 +111,27 @@ struct tegra_vgpu_channel_hwctx_params {
enum {
TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0,
TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE,
TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE,
TEGRA_VGPU_ATTRIB_COMPTAG_LINES,
TEGRA_VGPU_ATTRIB_GPC_COUNT,
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT,
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT,
TEGRA_VGPU_ATTRIB_PMC_BOOT_0,
TEGRA_VGPU_ATTRIB_L2_SIZE,
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH,
TEGRA_VGPU_ATTRIB_NUM_FBPS,
TEGRA_VGPU_ATTRIB_FBP_EN_MASK,
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP,
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC,
TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK,
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE,
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE,
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC,
TEGRA_VGPU_ATTRIB_LTC_COUNT,
TEGRA_VGPU_ATTRIB_TPC_COUNT,
TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT,
TEGRA_VGPU_ATTRIB_MAX_FREQ,
TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1,
TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2,
TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3,
TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7,
TEGRA_VGPU_ATTRIB_L2_SIZE = 8,
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9,
TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11,
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12,
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13,
TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14,
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15,
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16,
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17,
TEGRA_VGPU_ATTRIB_LTC_COUNT = 18,
TEGRA_VGPU_ATTRIB_TPC_COUNT = 19,
TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
TEGRA_VGPU_ATTRIB_MAX_FREQ = 21,
};
struct tegra_vgpu_attrib_params {
@@ -441,22 +441,22 @@ struct tegra_vgpu_cmd_msg {
enum {
TEGRA_VGPU_GR_INTR_NOTIFY = 0,
TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT,
TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY,
TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD,
TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS,
TEGRA_VGPU_GR_INTR_FECS_ERROR,
TEGRA_VGPU_GR_INTR_CLASS_ERROR,
TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD,
TEGRA_VGPU_GR_INTR_EXCEPTION,
TEGRA_VGPU_GR_INTR_SEMAPHORE,
TEGRA_VGPU_FIFO_INTR_PBDMA,
TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT,
TEGRA_VGPU_FIFO_INTR_MMU_FAULT,
TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE,
TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL,
TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE,
TEGRA_VGPU_GR_INTR_SM_EXCEPTION
TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1,
TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2,
TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3,
TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4,
TEGRA_VGPU_GR_INTR_FECS_ERROR = 5,
TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6,
TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7,
TEGRA_VGPU_GR_INTR_EXCEPTION = 8,
TEGRA_VGPU_GR_INTR_SEMAPHORE = 9,
TEGRA_VGPU_FIFO_INTR_PBDMA = 10,
TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11,
TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12,
TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13,
TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14,
TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15,
TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16,
};
struct tegra_vgpu_gr_intr_info {
@@ -498,18 +498,18 @@ struct tegra_vgpu_general_event_info {
enum {
TEGRA_VGPU_INTR_GR = 0,
TEGRA_VGPU_INTR_FIFO,
TEGRA_VGPU_INTR_CE2,
TEGRA_VGPU_NONSTALL_INTR_GR,
TEGRA_VGPU_NONSTALL_INTR_FIFO,
TEGRA_VGPU_NONSTALL_INTR_CE2
TEGRA_VGPU_INTR_FIFO = 1,
TEGRA_VGPU_INTR_CE2 = 2,
TEGRA_VGPU_NONSTALL_INTR_GR = 3,
TEGRA_VGPU_NONSTALL_INTR_FIFO = 4,
TEGRA_VGPU_NONSTALL_INTR_CE2 = 5,
};
enum {
TEGRA_VGPU_EVENT_INTR = 0,
TEGRA_VGPU_EVENT_ABORT,
TEGRA_VGPU_EVENT_FECS_TRACE,
TEGRA_VGPU_EVENT_CHANNEL,
TEGRA_VGPU_EVENT_ABORT = 1,
TEGRA_VGPU_EVENT_FECS_TRACE = 2,
TEGRA_VGPU_EVENT_CHANNEL = 3,
};
struct tegra_vgpu_intr_msg {