gpu: nvgpu: program ltc cg prod values after acr boot

Separate nvgpu_cg_blcg/slcg_fb_ltc_load_enable function
into nvgpu_cg_blcg/slcg_fb_load_enable and
nvgpu_cg_blcg/slcg_ltc_load_enable.

Program fb slcg/blcg prod values during fb init and
program ltc slcg/blcg prod values after acr boot to
have correct privilege for ltc cg programming.

Update unit tests to have sperate blcg/slcg hal for
fb and ltc programming.

Bug 3423549

Change-Id: Icdb45528abe1a3ab68a47f689310dee9a4fe9366
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2646039
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2021-12-22 11:25:42 -08:00
committed by mobile promotions
parent 4e98b53944
commit a7c1052024
9 changed files with 158 additions and 55 deletions

View File

@@ -41,6 +41,7 @@
#include <nvgpu/fb.h>
#include <nvgpu/device.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/power_features/cg.h>
#ifdef CONFIG_NVGPU_GSP_SCHEDULER
#include <nvgpu/gsp.h>
#endif
@@ -642,6 +643,14 @@ static int nvgpu_init_slcg_acb_load_gating_prod(struct gk20a *g)
return 0;
}
static int nvgpu_init_cg_ltc_load_gating_prod(struct gk20a *g)
{
nvgpu_cg_slcg_ltc_load_enable(g);
nvgpu_cg_blcg_ltc_load_enable(g);
return 0;
}
static int nvgpu_ipa_pa_rwsem_init(struct gk20a *g)
{
nvgpu_rwsem_init(&(g->ipa_pa_cache.ipa_pa_rw_lock));
@@ -879,6 +888,15 @@ int nvgpu_finalize_poweron(struct gk20a *g)
* in the init sequence and called after acr boot.
*/
NVGPU_INIT_TABLE_ENTRY(g->ops.fb.set_atomic_mode, NO_FLAG),
/**
* During acr boot, PLM for ltc clock gating registers
* will be lowered for nvgpu(PL0) write access. So,
* ltc clock gating programming is done after acr boot.
* Bug 3469873
*/
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_cg_ltc_load_gating_prod,
NO_FLAG),
#ifdef CONFIG_NVGPU_DGPU
NVGPU_INIT_TABLE_ENTRY(g->ops.sec2.init_sec2_support,
NVGPU_SUPPORT_SEC2_RTOS),