diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
index 0b7829e2f..dadec43ee 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
@@ -1022,7 +1022,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
 		goto boardobjgrp_pmucmdsend_exit;
 	}
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handlerparams.success, 1);
 	if (handlerparams.success == 0U) {
 		nvgpu_err(g, "could not process cmd");
diff --git a/drivers/gpu/nvgpu/common/ce2.c b/drivers/gpu/nvgpu/common/ce2.c
index 9520abeaf..67d028054 100644
--- a/drivers/gpu/nvgpu/common/ce2.c
+++ b/drivers/gpu/nvgpu/common/ce2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -105,7 +105,7 @@ int gk20a_ce_execute_ops(struct gk20a *g,
 			&ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset];
 
 		ret = gk20a_fence_wait(g, *prev_post_fence,
-				       gk20a_get_gr_idle_timeout(g));
+				       nvgpu_get_poll_timeout(g));
 
 		gk20a_fence_put(*prev_post_fence);
 		*prev_post_fence = NULL;
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c
index f21c7c989..2f7d4f171 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel.c
@@ -270,7 +270,7 @@ int gk20a_wait_channel_idle(struct channel_gk20a *ch)
 	bool channel_idle = false;
 	struct nvgpu_timeout timeout;
 
-	nvgpu_timeout_init(ch->g, &timeout, gk20a_get_gr_idle_timeout(ch->g),
+	nvgpu_timeout_init(ch->g, &timeout, nvgpu_get_poll_timeout(ch->g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 	do {
@@ -326,7 +326,7 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force)
 	struct gk20a *g = ch->g;
 	struct fifo_gk20a *f = &g->fifo;
 	struct vm_gk20a *ch_vm = ch->vm;
-	unsigned long timeout = gk20a_get_gr_idle_timeout(g);
+	unsigned long timeout = nvgpu_get_poll_timeout(g);
 	struct dbg_session_gk20a *dbg_s;
 	struct dbg_session_data *session_data, *tmp_s;
 	struct dbg_session_channel_data *ch_data, *tmp;
@@ -742,7 +742,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 	ch->ctxsw_timeout_accumulated_ms = 0;
 	ch->ctxsw_timeout_gpfifo_get = 0;
 	/* set gr host default timeout */
-	ch->ctxsw_timeout_max_ms = gk20a_get_gr_idle_timeout(g);
+	ch->ctxsw_timeout_max_ms = nvgpu_get_poll_timeout(g);
 	ch->ctxsw_timeout_debug_dump = true;
 	ch->unserviceable = false;
 
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 6d32edb47..0f5a546ae 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -411,7 +411,7 @@ int nvgpu_engine_wait_for_idle(struct gk20a *g)
 	host_num_engines =
 		 nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
-	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 	for (i = 0; i < host_num_engines; i++) {
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
index 361d071c5..2129d665e 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
@@ -201,7 +201,7 @@ int gk20a_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
 	int ret = -ETIMEDOUT;
 
-	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 	do {
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
index dd8d2fd89..d67de481a 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
@@ -78,7 +78,7 @@ int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
 	int ret = -ETIMEDOUT;
 
-	ret = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	ret = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 	if (ret != 0) {
 		return ret;
diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index aaaf1fcb6..4166b3aff 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -120,7 +120,7 @@ void nvgpu_gr_flush_channel_tlb(struct gk20a *g)
 u32 nvgpu_gr_get_idle_timeout(struct gk20a *g)
 {
 	return nvgpu_is_timeouts_enabled(g) ?
-		g->gr_idle_timeout_default : UINT_MAX;
+		g->poll_timeout_default : UINT_MAX;
 }
 
 int nvgpu_gr_init_fs_state(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/common/mm/vidmem.c b/drivers/gpu/nvgpu/common/mm/vidmem.c
index 7aec7c850..55b80c16b 100644
--- a/drivers/gpu/nvgpu/common/mm/vidmem.c
+++ b/drivers/gpu/nvgpu/common/mm/vidmem.c
@@ -120,12 +120,12 @@ static int __nvgpu_vidmem_do_clear_all(struct gk20a *g)
 		struct nvgpu_timeout timeout;
 
 		nvgpu_timeout_init(g, &timeout,
-				   gk20a_get_gr_idle_timeout(g),
+				   nvgpu_get_poll_timeout(g),
 				   NVGPU_TIMER_CPU_TIMER);
 
 		do {
 			err = gk20a_fence_wait(g, gk20a_fence_out,
-					       gk20a_get_gr_idle_timeout(g));
+					       nvgpu_get_poll_timeout(g));
 		} while (err == -ERESTARTSYS &&
 			 !nvgpu_timeout_expired(&timeout));
 
@@ -463,12 +463,12 @@ int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem)
 		struct nvgpu_timeout timeout;
 
 		nvgpu_timeout_init(g, &timeout,
-				   gk20a_get_gr_idle_timeout(g),
+				   nvgpu_get_poll_timeout(g),
 				   NVGPU_TIMER_CPU_TIMER);
 
 		do {
 			err = gk20a_fence_wait(g, gk20a_last_fence,
-					       gk20a_get_gr_idle_timeout(g));
+					       nvgpu_get_poll_timeout(g));
 		} while (err == -ERESTARTSYS &&
 			 !nvgpu_timeout_expired(&timeout));
 
diff --git a/drivers/gpu/nvgpu/common/nvlink/minion.c b/drivers/gpu/nvgpu/common/nvlink/minion.c
index 4b1b3b6d7..79004814f 100644
--- a/drivers/gpu/nvgpu/common/nvlink/minion.c
+++ b/drivers/gpu/nvgpu/common/nvlink/minion.c
@@ -89,7 +89,7 @@ int nvgpu_nvlink_minion_load(struct gk20a *g)
 		goto exit;
 	}
 
-	err = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 		NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		nvgpu_err(g, "Minion boot timeout init failed");
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
index fbb2329c6..7f170acff 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
@@ -115,7 +115,7 @@ int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload)
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 	if (handler.success == 0U) {
 		nvgpu_err(g, "rpc call to load Effective avg clk domain freq failed");
@@ -176,7 +176,7 @@ int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32 clkDomainMask) {
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 	if (handler.success == 0U) {
 		nvgpu_err(g, "rpc call to get clk frequency average failed");
@@ -283,7 +283,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 
 	if (handler.success == 0U) {
@@ -346,7 +346,7 @@ int nvgpu_clk_pmu_vin_load(struct gk20a *g)
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 
 	if (handler.success == 0U) {
@@ -408,7 +408,7 @@ int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g)
 	}
 
 	(void) pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 
 	if (handler.success == 0U) {
@@ -558,7 +558,7 @@ static int clk_pmu_vf_inject(struct gk20a *g,
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handler.success, 1);
 
 	if (handler.success == 0U) {
diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
index a24ab673b..804fffa3b 100644
--- a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
@@ -274,7 +274,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
 			PMU_COMMAND_QUEUE_HPQ,
 			nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq);
 
-		pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+		pmu_wait_message_cond(&g->pmu, nvgpu_get_poll_timeout(g),
 			&ack_status, 1);
 		if (ack_status == 0U) {
 			status = -EINVAL;
@@ -310,7 +310,7 @@ int nvgpu_lpwr_post_init(struct gk20a *g)
 		PMU_COMMAND_QUEUE_LPQ,
 		nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq);
 
-	pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+	pmu_wait_message_cond(&g->pmu, nvgpu_get_poll_timeout(g),
 		&ack_status, 1);
 	if (ack_status == 0U) {
 		status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
index f5abb0d39..2d9e0b18e 100644
--- a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
@@ -98,7 +98,7 @@ static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
 	}
 
 	if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) {
-		pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+		pmu_wait_message_cond(&g->pmu, nvgpu_get_poll_timeout(g),
 			&success, 1);
 		if (success == 0U) {
 			status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
index 814157e2b..3c7012e85 100644
--- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
@@ -334,7 +334,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
 	/* wait if on_pending */
 	else if (pmu->pmu_pg.elpg_stat == PMU_ELPG_STAT_ON_PENDING) {
 
-		pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
+		pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g),
 				      &pmu->pmu_pg.elpg_stat, PMU_ELPG_STAT_ON);
 
 		if (pmu->pmu_pg.elpg_stat != PMU_ELPG_STAT_ON) {
@@ -395,7 +395,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
 			}
 
 			pmu_wait_message_cond(pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				ptr, PMU_ELPG_STAT_OFF);
 			if (*ptr != PMU_ELPG_STAT_OFF) {
 				nvgpu_err(g, "ELPG_DISALLOW_ACK failed");
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
index dfa9ae1f6..b7f1e3cc3 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
@@ -136,7 +136,7 @@ static int pmgr_pmu_set_object(struct gk20a *g,
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handlerparams.success, 1);
 
 	if (handlerparams.success == 0U) {
@@ -439,7 +439,7 @@ int pmgr_pmu_pwr_devices_query_blocking(
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handlerparams.success, 1);
 
 	if (handlerparams.success == 0U) {
@@ -483,7 +483,7 @@ static int pmgr_pmu_load_blocking(struct gk20a *g)
 	}
 
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&handlerparams.success, 1);
 
 	if (handlerparams.success == 0U) {
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 0fd89a524..63039b5d2 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -283,7 +283,7 @@ int nvgpu_init_pmu_support(struct gk20a *g)
 		 * hitting breakpoint due to PMU halt
 		 */
 		err = nvgpu_falcon_clear_halt_intr_status(&g->pmu.flcn,
-			gk20a_get_gr_idle_timeout(g));
+			nvgpu_get_poll_timeout(g));
 		if (err != 0) {
 			goto exit;
 		}
@@ -639,7 +639,7 @@ int nvgpu_pmu_wait_ready(struct gk20a *g)
 	int status = 0;
 
 	status = pmu_wait_message_cond_status(&g->pmu,
-		gk20a_get_gr_idle_timeout(g),
+		nvgpu_get_poll_timeout(g),
 		&g->pmu.pmu_ready, (u8)true);
 	if (status != 0) {
 		nvgpu_err(g, "PMU is not ready yet");
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c
index 039e5e881..de2172a34 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c
@@ -575,7 +575,7 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
 	gk20a_dbg_pmu(g, "cmd post ZBC_TABLE_UPDATE");
 	nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
 			   pmu_handle_zbc_msg, pmu, &seq);
-	pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
+	pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g),
 			      &pmu->pmu_pg.zbc_save_done, 1);
 	if (!pmu->pmu_pg.zbc_save_done) {
 		nvgpu_err(g, "ZBC save timeout");
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
index a0d6d19f8..86649d08b 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
@@ -232,7 +232,7 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 {
 	int  err = 0;
 	u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
-	u32 timeout = gk20a_get_gr_idle_timeout(g);
+	u32 timeout = nvgpu_get_poll_timeout(g);
 
 	/* GM20B PMU supports loading FECS only */
 	if (!(falconidmask == BIT32(FALCON_ID_FECS))) {
@@ -241,7 +241,7 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	/* check whether pmu is ready to bootstrap lsf if not wait for it */
 	if (!g->pmu_lsf_pmu_wpr_init_done) {
 		pmu_wait_message_cond(&g->pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				&g->pmu_lsf_pmu_wpr_init_done, 1);
 		/* check again if it still not ready indicate an error */
 		if (!g->pmu_lsf_pmu_wpr_init_done) {
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
index bb0e40093..399f50579 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
@@ -156,7 +156,7 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	/* check whether pmu is ready to bootstrap lsf if not wait for it */
 	if (!g->pmu_lsf_pmu_wpr_init_done) {
 		pmu_wait_message_cond(&g->pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				&g->pmu_lsf_pmu_wpr_init_done, 1);
 		/* check again if it still not ready indicate an error */
 		if (!g->pmu_lsf_pmu_wpr_init_done) {
@@ -168,7 +168,7 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	gp106_pmu_load_multiple_falcons(g, falconidmask, flags);
 	nvgpu_assert(falconidmask < U32(U8_MAX));
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&g->pmu_lsf_loaded_falcon_id, U8(falconidmask));
 	if (g->pmu_lsf_loaded_falcon_id != falconidmask) {
 		return -ETIMEDOUT;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
index 5db27b1c0..cdda34780 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
@@ -187,7 +187,7 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	/* check whether pmu is ready to bootstrap lsf if not wait for it */
 	if (!g->pmu_lsf_pmu_wpr_init_done) {
 		pmu_wait_message_cond(&g->pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				&g->pmu_lsf_pmu_wpr_init_done, 1);
 		/* check again if it still not ready indicate an error */
 		if (!g->pmu_lsf_pmu_wpr_init_done) {
@@ -199,7 +199,7 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
 	nvgpu_assert(falconidmask <= U8_MAX);
 	pmu_wait_message_cond(&g->pmu,
-			gk20a_get_gr_idle_timeout(g),
+			nvgpu_get_poll_timeout(g),
 			&g->pmu_lsf_loaded_falcon_id, (u8)falconidmask);
 	if (g->pmu_lsf_loaded_falcon_id != falconidmask) {
 		return -ETIMEDOUT;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gv100.c b/drivers/gpu/nvgpu/common/pmu/pmu_gv100.c
index 5dec508bb..855503ef0 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_gv100.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_gv100.c
@@ -1,7 +1,7 @@
 /*
  * GV100 PMU
  *
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -67,7 +67,7 @@ int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 	/* check whether pmu is ready to bootstrap lsf if not wait for it */
 	if (!g->pmu_lsf_pmu_wpr_init_done) {
 		pmu_wait_message_cond(&g->pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				&g->pmu_lsf_pmu_wpr_init_done, 1);
 		/* check again if it still not ready indicate an error */
 		if (!g->pmu_lsf_pmu_wpr_init_done) {
@@ -90,7 +90,7 @@ int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 		goto exit;
 	}
 
-	pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+	pmu_wait_message_cond(&g->pmu, nvgpu_get_poll_timeout(g),
 		&g->pmu_lsf_loaded_falcon_id, 1);
 
 	if (g->pmu_lsf_loaded_falcon_id != 1U) {
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index 165faaf8c..76fe4b4d0 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -1459,7 +1459,7 @@ int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc,
 	 */
 	if (is_copy_back) {
 		/* wait till RPC execute in PMU & ACK */
-		pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
+		pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g),
 			&rpc_payload->complete, 1);
 		/* copy back data to caller */
 		nvgpu_memcpy((u8 *)rpc, (u8 *)rpc_buff, size_rpc);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
index 5f118b25c..08dcba175 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
@@ -490,7 +490,7 @@ int nvgpu_pmu_perfmon_get_samples_rpc(struct nvgpu_pmu *pmu)
 		nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);
 	}
 
-	pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
+	pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g),
 				      &pmu->perfmon_query, 1);
 
 	return status;
diff --git a/drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c b/drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c
index cd3bcc596..fea59393e 100644
--- a/drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c
@@ -109,7 +109,7 @@ static int therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 		handlerparams = (struct therm_pmucmdhandler_params*)cb_param;
 
 		pmu_wait_message_cond(&g->pmu,
-				gk20a_get_gr_idle_timeout(g),
+				nvgpu_get_poll_timeout(g),
 				&handlerparams->success, 1);
 
 		if (handlerparams->success == 0U) {
diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c
index 9c8daf267..520fe731d 100644
--- a/drivers/gpu/nvgpu/common/sec2/sec2.c
+++ b/drivers/gpu/nvgpu/common/sec2/sec2.c
@@ -257,7 +257,7 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
 		nvgpu_err(g, "command post failed");
 	}
 
-	err = nvgpu_sec2_wait_message_cond(sec2, gk20a_get_gr_idle_timeout(g),
+	err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g),
 		&command_ack, true);
 	if (err != 0) {
 		nvgpu_err(g, "command ack receive failed");
@@ -274,7 +274,7 @@ int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
 	nvgpu_log_fn(g, " ");
 
 	nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait");
-	err = nvgpu_sec2_wait_message_cond(&g->sec2, gk20a_get_gr_idle_timeout(g),
+	err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g),
 			&g->sec2.sec2_ready, true);
 	if (err != 0){
 		nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d",
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5c5cdece6..cda8075d4 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -319,7 +319,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
 		delay = GR_IDLE_CHECK_DEFAULT;
 	}
 
-	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 	while (check == WAIT_UCODE_LOOP) {
@@ -5058,7 +5058,7 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
 	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
 		"GPC%d TPC%d SM%d: locking down SM", gpc, tpc, sm);
 
-	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 	/* wait for the sm to lock down */
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 0067a1ac7..30b73a2d4 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -79,7 +79,7 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
 		}
 	}
 
-	ret = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	ret = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 	if (ret != 0) {
 		nvgpu_err(g, "timeout init failed err=%d", ret);
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c
index 0024de2a9..72009400b 100644
--- a/drivers/gpu/nvgpu/gp106/bios_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/bios_gp106.c
@@ -132,7 +132,7 @@ int gp106_bios_devinit(struct gk20a *g)
 	}
 
 	err = nvgpu_falcon_clear_halt_intr_status(&g->pmu.flcn,
-		gk20a_get_gr_idle_timeout(g));
+		nvgpu_get_poll_timeout(g));
 	if (err != 0) {
 		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
 		goto out;
@@ -191,7 +191,7 @@ int gp106_bios_preos(struct gk20a *g)
 	}
 
 	err = nvgpu_falcon_clear_halt_intr_status(&g->pmu.flcn,
-			gk20a_get_gr_idle_timeout(g));
+			nvgpu_get_poll_timeout(g));
 	if (err != 0) {
 		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
 		goto out;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index fc13e8901..f0b015dfb 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1519,7 +1519,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
 
 		nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
 			"CILP preempt pending, waiting %u msecs for preemption",
-			gk20a_get_gr_idle_timeout(g));
+			nvgpu_get_poll_timeout(g));
 
 		tsg = tsg_gk20a_from_ch(cilp_preempt_pending_ch);
 		if (tsg == NULL) {
@@ -1529,7 +1529,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
 
 		gr_ctx = tsg->gr_ctx;
 
-		nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+		nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 				   NVGPU_TIMER_CPU_TIMER);
 		do {
 			if (!gr_ctx->cilp_preempt_pending) {
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 8a732df51..72c82faab 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2848,7 +2848,7 @@ int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g,
 	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
 		"GPC%d TPC%d: locking down SM%d", gpc, tpc, sm);
 
-	err = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		nvgpu_err(g, "timeout_init failed: %d", err);
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
index 6d15944d8..bb5b30c5e 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
@@ -361,7 +361,7 @@ void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g,
 		struct nvgpu_timeout timeout;
 		u32 delay = GR_IDLE_CHECK_DEFAULT;
 
-		nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+		nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
 		reg_val &= (~(fb_mmu_fault_buffer_size_enable_m()));
diff --git a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
index 02584af04..ef180a512 100644
--- a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
+++ b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
@@ -105,7 +105,7 @@ static int gv100_nvlink_minion_command_complete(struct gk20a *g, u32 link_id)
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
 	int err = 0;
 
-	err = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
 				NVGPU_TIMER_CPU_TIMER);
 	if (err != 0) {
 		nvgpu_err(g, "Minion cmd complete timeout init failed");
diff --git a/drivers/gpu/nvgpu/include/nvgpu/defaults.h b/drivers/gpu/nvgpu/include/nvgpu/defaults.h
index cae380a74..d73111fa6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/defaults.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/defaults.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,7 @@
 /*
  * Default timeout used for channel watchdog and ctxsw timeout.
  */
-#define NVGPU_DEFAULT_GR_IDLE_TIMEOUT	3000
+#define NVGPU_DEFAULT_POLL_TIMEOUT_MS	3000
 
 #define NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT 500
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index f59c568b3..66fad74dd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1905,7 +1905,7 @@ struct gk20a {
 #ifdef CONFIG_DEBUG_FS
 	struct railgate_stats pstats;
 #endif
-	u32 gr_idle_timeout_default;
+	u32 poll_timeout_default;
 	bool timeouts_disabled_by_user;
 
 	unsigned int ch_wdt_init_limit_ms;
@@ -2140,10 +2140,10 @@ static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g)
 	return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0;
 }
 
-static inline u32 gk20a_get_gr_idle_timeout(struct gk20a *g)
+static inline u32 nvgpu_get_poll_timeout(struct gk20a *g)
 {
 	return nvgpu_is_timeouts_enabled(g) ?
-		g->gr_idle_timeout_default : UINT_MAX;
+		g->poll_timeout_default : U32_MAX;
 }
 
 #define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
diff --git a/drivers/gpu/nvgpu/os/linux/debug.c b/drivers/gpu/nvgpu/os/linux/debug.c
index 5c36a7878..2ad01bbcc 100644
--- a/drivers/gpu/nvgpu/os/linux/debug.c
+++ b/drivers/gpu/nvgpu/os/linux/debug.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2019 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -372,10 +372,10 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
 				 l->debugfs,
 				 &g->mm.ltc_enabled_target);
 
-	l->debugfs_gr_idle_timeout_default =
-			debugfs_create_u32("gr_idle_timeout_default_us",
+	l->debugfs_poll_timeout_default =
+			debugfs_create_u32("poll_timeout_default_ms",
 					S_IRUGO|S_IWUSR, l->debugfs,
-					 &g->gr_idle_timeout_default);
+					 &g->poll_timeout_default);
 	l->debugfs_timeouts_enabled =
 			debugfs_create_file("timeouts_enabled",
 					S_IRUGO|S_IWUSR,
diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c
index 78b0da588..911622ceb 100644
--- a/drivers/gpu/nvgpu/os/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/os/linux/driver_common.c
@@ -116,11 +116,11 @@ static void nvgpu_init_timeout(struct gk20a *g)
 	nvgpu_atomic_set(&g->timeouts_disabled_refcount, 0);
 
 	if (nvgpu_platform_is_silicon(g)) {
-		g->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT;
+		g->poll_timeout_default = NVGPU_DEFAULT_POLL_TIMEOUT_MS;
 	} else if (nvgpu_platform_is_fpga(g)) {
-		g->gr_idle_timeout_default = GK20A_TIMEOUT_FPGA;
+		g->poll_timeout_default = GK20A_TIMEOUT_FPGA;
 	} else {
-		g->gr_idle_timeout_default = (u32)ULONG_MAX;
+		g->poll_timeout_default = (u32)ULONG_MAX;
 	}
 	g->ch_wdt_init_limit_ms = platform->ch_wdt_init_limit_ms;
 	g->ctxsw_timeout_period_ms = CTXSW_TIMEOUT_PERIOD_MS;
diff --git a/drivers/gpu/nvgpu/os/linux/os_linux.h b/drivers/gpu/nvgpu/os/linux/os_linux.h
index 8ef81c8d7..83d71fdc6 100644
--- a/drivers/gpu/nvgpu/os/linux/os_linux.h
+++ b/drivers/gpu/nvgpu/os/linux/os_linux.h
@@ -144,7 +144,7 @@ struct nvgpu_os_linux {
 
 	struct dentry *debugfs_ltc_enabled;
 	struct dentry *debugfs_timeouts_enabled;
-	struct dentry *debugfs_gr_idle_timeout_default;
+	struct dentry *debugfs_poll_timeout_default;
 	struct dentry *debugfs_disable_bigpage;
 
 	struct dentry *debugfs_timeslice_low_priority_us;
diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
index 4ffcdf535..116c4ae7c 100644
--- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
+++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
@@ -428,7 +428,7 @@ int vgpu_probe(struct platform_device *pdev)
 	dma_set_mask(dev, platform->dma_mask);
 	dma_set_coherent_mask(dev, platform->dma_mask);
 
-	gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT;
+	gk20a->poll_timeout_default = NVGPU_DEFAULT_POLL_TIMEOUT_MS;
 	gk20a->timeouts_disabled_by_user = false;
 	nvgpu_atomic_set(&gk20a->timeouts_disabled_refcount, 0);