From a8866825d27544238002e0d33949b487ed3cbab7 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 2 Dec 2019 11:44:02 +0530 Subject: [PATCH] gpu: nvgpu: fix the doxygen comments due to ECC and MC refactoring changes nvgpu_mc_log_pending_intrs is debugging related function hence compile out that and related functionality under CONFIG_NVGPU_NON_FUSA. nvgpu_mc_intr_enable is applicable for older chips hence compile out under CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Update BUS, CE, ECC, FIFO, MC, PRIV_RING, GR, LTC, FB, PMU units' doxygen comments based on recent ECC and MC refactoring. JIRA NVGPU-4439 Change-Id: I337318683d6311b9c2b5748f2fb07dff29a6584f Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2252853 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 4 ++ drivers/gpu/nvgpu/common/ltc/ltc.c | 1 - drivers/gpu/nvgpu/common/mc/mc.c | 2 + drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 4 ++ drivers/gpu/nvgpu/include/nvgpu/ce.h | 1 + drivers/gpu/nvgpu/include/nvgpu/ecc.h | 8 +++- drivers/gpu/nvgpu/include/nvgpu/fifo.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops_bus.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gops_fb.h | 4 ++ drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/gops_mc.h | 38 ++++++++++--------- .../gpu/nvgpu/include/nvgpu/gops_priv_ring.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/gr/gr.h | 9 ++++- drivers/gpu/nvgpu/include/nvgpu/ltc.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/mc.h | 18 ++++----- drivers/gpu/nvgpu/include/nvgpu/mm.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 3 +- userspace/units/init/nvgpu-init.c | 2 - 18 files changed, 72 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 1c6a924a5..f0edc63df 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -66,7 +66,9 @@ void nvgpu_check_gpu_state(struct gk20a *g) static void gk20a_mask_interrupts(struct gk20a *g) { nvgpu_mc_intr_mask(g); +#ifdef CONFIG_NVGPU_NON_FUSA nvgpu_mc_log_pending_intrs(g); +#endif } #ifndef CONFIG_NVGPU_RECOVERY @@ -479,11 +481,13 @@ static int nvgpu_init_interrupt_setup(struct gk20a *g) */ nvgpu_mc_intr_mask(g); +#ifdef CONFIG_NVGPU_NON_FUSA /** * For certain chips like gm20b, there is global interrupt control in * registers mc_intr_en_*_r. Program them here upfront. */ nvgpu_mc_intr_enable(g); +#endif return 0; } diff --git a/drivers/gpu/nvgpu/common/ltc/ltc.c b/drivers/gpu/nvgpu/common/ltc/ltc.c index 212e12cd1..f7f9862df 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc.c @@ -40,7 +40,6 @@ void nvgpu_ltc_remove_support(struct gk20a *g) g->ltc = NULL; } - int nvgpu_init_ltc_support(struct gk20a *g) { struct nvgpu_ltc *ltc = g->ltc; diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c index 7a1e4b17b..d1fe3cd69 100644 --- a/drivers/gpu/nvgpu/common/mc/mc.c +++ b/drivers/gpu/nvgpu/common/mc/mc.c @@ -76,6 +76,7 @@ void nvgpu_mc_intr_mask(struct gk20a *g) } } +#ifdef CONFIG_NVGPU_NON_FUSA void nvgpu_mc_log_pending_intrs(struct gk20a *g) { if (g->ops.mc.log_pending_intrs != NULL) { @@ -93,6 +94,7 @@ void nvgpu_mc_intr_enable(struct gk20a *g) nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); } } +#endif void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable) { diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 356d5b9c6..0c89fac64 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1268,7 +1268,9 @@ static const struct gpu_ops gv11b_ops = { .mc = { .get_chip_details = gm20b_get_chip_details, .intr_mask = mc_gp10b_intr_mask, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA .intr_enable = NULL, +#endif .intr_stall_unit_config = mc_gp10b_intr_stall_unit_config, .intr_nonstall_unit_config = mc_gp10b_intr_nonstall_unit_config, .isr_stall = mc_gp10b_isr_stall, @@ -1283,7 +1285,9 @@ static const struct gpu_ops gv11b_ops = { .disable = gm20b_mc_disable, .reset = gm20b_mc_reset, .is_intr1_pending = mc_gp10b_is_intr1_pending, +#ifdef CONFIG_NVGPU_NON_FUSA .log_pending_intrs = mc_gp10b_log_pending_intrs, +#endif .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, .is_stall_and_eng_intr_pending = gv11b_mc_is_stall_and_eng_intr_pending, diff --git a/drivers/gpu/nvgpu/include/nvgpu/ce.h b/drivers/gpu/nvgpu/include/nvgpu/ce.h index b2c259472..6348b890e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ce.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ce.h @@ -77,6 +77,7 @@ struct gk20a; * - Load Second Level Clock Gating (SLCG) configuration for copy engine. * - Load Block Level Clock Gating (BLCG) configuration for copy engine. * - Initialize configuration options for LCEs. FORCE_BARRIERS_NPL is set. + * - Enable CE engines stalling and non-stalling interrupts at MC level. * * @return 0 in case of success, < 0 in case of failure. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/ecc.h b/drivers/gpu/nvgpu/include/nvgpu/ecc.h index e0bf3e4d5..213048b46 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ecc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ecc.h @@ -277,7 +277,7 @@ int nvgpu_ecc_counter_init(struct gk20a *g, * @brief Concatenates the error counter to status list. * * @param g [in] The GPU driver struct. - * @param stat [out] Pointer to error counter. + * @param stat [in] Pointer to error counter. * * The counter is added to the status_list of struct nvgpu_ecc. */ @@ -298,6 +298,8 @@ void nvgpu_ecc_free(struct gk20a *g); * * @param g [in] The GPU driver struct. * + * Initializes the error counters list g->ecc.stats_list. + * * @return 0 in case of success, less than 0 for failure. */ int nvgpu_ecc_init_support(struct gk20a *g); @@ -306,6 +308,8 @@ int nvgpu_ecc_init_support(struct gk20a *g); * @brief Destroys, frees up memory allocated to ecc/parity error counters. * * @param g [in] The GPU driver struct. + * + * Frees up memory allocated to ecc error counters for all units. */ void nvgpu_ecc_remove_support(struct gk20a *g); @@ -313,6 +317,8 @@ void nvgpu_ecc_remove_support(struct gk20a *g); * @brief Finish ECC support initialization. * * @param g [in] The GPU driver struct. + * + * Sets ecc.initialized to true. */ int nvgpu_ecc_finalize_support(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h index a37e859fa..8be9c7096 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h @@ -501,7 +501,7 @@ const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index); * @param g [in] The GPU driver struct. * * Suspending FIFO will disable BAR1 snooping (if supported by h/w) and also - * FIFO interrupts. + * FIFO stalling and non-stalling interrupts at FIFO unit and MC level. */ int nvgpu_fifo_suspend(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h b/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h index 83c9ba8a1..dd3c9a35c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h @@ -43,6 +43,7 @@ struct gops_bus { * * @param g [in] Pointer to GPU driver struct. * + * This function enables bus unit stalling interrupt at MC level. * This function enables interrupts for following errors: * NV_PBUS_INTR_EN_0_PRI_SQUASH - Error due to request sent to * while h/w block is in reset. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_fb.h b/drivers/gpu/nvgpu/include/nvgpu/gops_fb.h index b09a2865a..e0c028540 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_fb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_fb.h @@ -44,6 +44,7 @@ struct gops_fb_intr { * * @param g [in] Pointer to GPU driver struct. * + * This function enable the stalling interrupt for fb unit at MC level. * This function enables following fb hub interrupts. * MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC errors. * MMU_NONREPLAYABLE_FAULT_NOTIFY: non-replayable fault happened. @@ -59,6 +60,8 @@ struct gops_fb_intr { * @param g [in] Pointer to GPU driver struct. * * This function disables fb hub interrupts enabled in enable. + * This function disables the stalling interrupt for fb unit at + * MC level. */ void (*disable)(struct gk20a *g); @@ -145,6 +148,7 @@ struct gops_fb { * - configures address that is used for issuing flush reads to system memory. * - initializes mmu debugger buffer. + * - enables fb unit stalling interrupt at MC level. * - enables fb interrupts related to mmu faults. */ void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h b/drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h index a6b235548..a8dbb173d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h @@ -123,7 +123,8 @@ struct gops_fifo { * - Set BLCG settings for FIFO. * - Set FB timeout for FIFO initiated requests. * - Setup PBDMA timeouts. - * - Enable stalling and non-stalling interrupts. + * - Enable FIFO unit stalling and non-stalling interrupts at MC level. + * - Enable FIFO stalling and non-stalling interrupts. * * @return 0 in case of success, < 0 in case of failure. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h index 23936e2ac..58ed7beeb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h @@ -258,28 +258,13 @@ struct gops_mc { */ u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit); - /** - * @brief Interrupt Service Routine (ISR) for handling the Level Two - * Cache (LTC) interrupts. - * - * @param g [in] The GPU driver struct. - * - * This function is invoked to handle the LTC interrupts from - * #isr_stall. - * - * Steps: - * - Read mc_intr_ltc_r register to get the interrupts status for LTCs. - * - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g) - * - If interrupt bitmask is set in the interrupts status register - * - Invoke g->ops.ltc.intr.isr. - */ - void (*ltc_isr)(struct gk20a *g); - /** @cond DOXYGEN_SHOULD_SKIP_THIS */ void (*intr_mask)(struct gk20a *g); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA void (*intr_enable)(struct gk20a *g); +#endif void (*intr_stall_unit_config)(struct gk20a *g, u32 unit, bool enable); @@ -308,7 +293,9 @@ struct gops_mc { bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); +#ifdef CONFIG_NVGPU_NON_FUSA void (*log_pending_intrs)(struct gk20a *g); +#endif void (*fb_reset)(struct gk20a *g); @@ -317,6 +304,23 @@ struct gops_mc { void (*fbpa_isr)(struct gk20a *g); #endif + /** + * @brief Interrupt Service Routine (ISR) for handling the Level Two + * Cache (LTC) interrupts. + * + * @param g [in] The GPU driver struct. + * + * This function is invoked to handle the LTC interrupts from + * #isr_stall. + * + * Steps: + * - Read mc_intr_ltc_r register to get the interrupts status for LTCs. + * - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g) + * - If interrupt bitmask is set in the interrupts status register + * - Invoke g->ops.ltc.intr.isr. + */ + void (*ltc_isr)(struct gk20a *g); + /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h index 26d5160da..2a6e635e9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h @@ -48,7 +48,8 @@ struct gops_priv_ring { * This function loads slcg priv ring prod values through * #nvgpu_cg_slcg_priring_load_enable, then initiate priv ring * enumeration and wait for priv ring enumeration complete to - * accept s/w register. + * accept s/w register. This function then enables the PRIV_RING + * unit stalling interrupt at MC level. * * @return 0 in case of success, < 0 in case of failure. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h index 7c3a82756..c4f828a4c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h @@ -201,9 +201,12 @@ int nvgpu_gr_enable_hw(struct gk20a *g); * functionality. This includes: * - Initializing context switch ucode. * - Reading Golden context image size from FECS micro controller. - * - Allocating memory for all internal data structures. + * - Allocating memory for all internal data structures such as GR ctx desc + * and ECC. * - Allocating global context buffers. * - Initializing GR engine h/w registers to known good values. + * - Enabling GR engine stalling and non-stalling interrupts and exceptions + * at GR unit and MC level. * - Reading GR engine configuration (like number of GPC/TPC/SM etc) * after considering floorsweeping. * @@ -263,7 +266,9 @@ u32 nvgpu_gr_get_no_of_sm(struct gk20a *g); * * This function is typically called while preparing for GPU power off. * This function makes sure that GR engine is idle before power off. - * It will also disable all GR engine interrupts and exceptions. + * It will also disable all GR engine stalling and non-stalling + * interrupts and exceptions at GR unit level and GR engine + * stalling and non-stalling interrupts at MC level. * * @return 0 in case of success, < 0 in case of failure. * @retval -EAGAIN if GR engine idle wait times out. diff --git a/drivers/gpu/nvgpu/include/nvgpu/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/ltc.h index 49fdd9a42..d392fa22f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ltc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ltc.h @@ -94,7 +94,9 @@ void nvgpu_ltc_ecc_free(struct gk20a *g); * @param g [in] Pointer to GPU driver struct. * * This function reads ltc unit info from GPU h/w and stores - * it in #nvgpu_ltc structure. + * it in #nvgpu_ltc structure. This function allocates memory + * to track the ecc error counts for the LTC unit and enables + * LTC unit interrupts and stalling interrupt at MC level. * * @return 0 in case of success, < 0 in case of failure. * @retval -ENOMEM if memory allocation for #nvgpu_ltc fails. diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h index e4a87efd3..2f48582ac 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h @@ -295,9 +295,10 @@ void nvgpu_wait_for_deferred_interrupts(struct gk20a *g); */ void nvgpu_mc_intr_mask(struct gk20a *g); +#ifdef CONFIG_NVGPU_NON_FUSA void nvgpu_mc_log_pending_intrs(struct gk20a *g); - void nvgpu_mc_intr_enable(struct gk20a *g); +#endif /** * @brief Enable the stalling interrupts for GPU unit at the master @@ -325,8 +326,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g); * enabling that unit's interrupts. * * Steps: - * - Get the interrupt bitmask for \a unit. * - Acquire the spinlock g->mc.intr_lock. + * - Get the interrupt bitmask for \a unit. * - If interrupt is to be enabled * - Set interrupt bitmask in * #intr_mask_restore[#NVGPU_MC_INTR_STALLING]. @@ -367,8 +368,8 @@ void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable); * enabling that unit's interrupts. * * Steps: - * - Get the interrupt bitmask for \a unit. * - Acquire the spinlock g->mc.intr_lock. + * - Get the interrupt bitmask for \a unit. * - If interrupt is to be enabled * - Set interrupt bitmask in * #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]. @@ -409,10 +410,9 @@ void nvgpu_mc_intr_stall_pause(struct gk20a *g); * * Steps: * - Acquire the spinlock g->mc.intr_lock. - * - Enable the stalling interrupts as configured during #intr_enable. - * Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the - * stalling interrupts enable set register - * (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)). + * - Enable the stalling interrupts as configured during #intr_stall_unit_config + * Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling + * interrupts enable set register (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)). * - Release the spinlock g->mc.intr_lock. */ void nvgpu_mc_intr_stall_resume(struct gk20a *g); @@ -443,8 +443,8 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g); * * Steps: * - Acquire the spinlock g->mc.intr_lock. - * - Enable the non-stalling interrupts as configured during - * #intr_enable. + * - Enable the stalling interrupts as configured during + * #intr_nonstall_unit_config. * Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING] * to the non-stalling interrupts enable set register * (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)). diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h index f9becdf3e..bab4ff869 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h @@ -528,6 +528,7 @@ void nvgpu_init_mm_ce_context(struct gk20a *g); * - Allocates and initializes the PMU instance block. * - Initializes the GMMU virtual memory region for CE. * - Allocates the GMMU debug write and read buffer (4K size). + * - Allocates ECC counters for fb and fbpa units. * - MM H/W setup: * - Configures the GMMU debug buffer location in fbhubmmu register. * - Enables the fbhubmmu mc interrupt. @@ -613,7 +614,7 @@ void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block); * - Flushes the FB and L2. Then, waits for completion (by polling) * upto polling timeout. * - Invalidate L2. - * - Disable the fbhubmmu mc interrupt. + * - Disable the fbhubmmu mc stalling interrupt and unit interrupts. * - Disable the mmu fault buffer h/w setup. * * @return 0 in case of success, < 0 in case of failure. diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index dc52d5d7f..785ad5108 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -370,7 +370,8 @@ int nvgpu_pmu_reset(struct gk20a *g); * Initializes PMU unit data struct in the GPU driver based on detected chip. * Allocate memory for #nvgpu_pmu data struct & set PMU Engine h/w properties, * PMU RTOS supporting data structs & ops of the PMU unit by populating data - * based on the detected chip. + * based on the detected chip. Allocates memory for ECC counters for PMU + * unit. * * @return 0 in case of success, < 0 in case of failure. */ diff --git a/userspace/units/init/nvgpu-init.c b/userspace/units/init/nvgpu-init.c index e25759fec..2e6085c88 100644 --- a/userspace/units/init/nvgpu-init.c +++ b/userspace/units/init/nvgpu-init.c @@ -656,7 +656,6 @@ int test_poweroff(struct unit_module *m, struct gk20a *g, void *args) simple_init_func_ptrs_count = i; g->ops.clk.suspend_clk_support = no_return; - g->ops.mc.log_pending_intrs = no_return; g->ops.mc.intr_mask = no_return; g->ops.falcon.falcon_sw_free = no_return_u32_param; @@ -678,7 +677,6 @@ int test_poweroff(struct unit_module *m, struct gk20a *g, void *args) /* Cover branches for NULL ptr checks */ g->ops.mc.intr_mask = NULL; - g->ops.mc.log_pending_intrs = NULL; g->ops.channel.suspend_all_serviceable_ch = NULL; g->ops.clk.suspend_clk_support = NULL; err = nvgpu_prepare_poweroff(g);