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gpu: nvgpu: reorganization of MC interrupts control

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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-09-11 14:57:19 +05:30
committed by Alex Waterman
parent daf5475f50
commit a8c9c800cd
49 changed files with 752 additions and 411 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/gpu/nvgpu/common/init/nvgpu_init.c
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@@ -65,13 +65,8 @@ void nvgpu_check_gpu_state(struct gk20a *g)
static void gk20a_mask_interrupts(struct gk20a *g)
{
if (g->ops.mc.intr_mask != NULL) {
g->ops.mc.intr_mask(g);
}
if (g->ops.mc.log_pending_intrs != NULL) {
g->ops.mc.log_pending_intrs(g);
}
nvgpu_mc_intr_mask(g);
nvgpu_mc_log_pending_intrs(g);
}
#ifndef CONFIG_NVGPU_RECOVERY
@@ -474,6 +469,22 @@ static int nvgpu_init_syncpt_mem(struct gk20a *g)
return 0;
}
static int nvgpu_init_interrupt_setup(struct gk20a *g)
{
/**
* Disable all interrupts at the start.
*/
nvgpu_mc_intr_mask(g);
/**
* For certain chips like gm20b, there is global interrupt control in
* registers mc_intr_en_*_r. Program them here upfront.
*/
nvgpu_mc_intr_enable(g);
return 0;
}
typedef int (*nvgpu_init_func_t)(struct gk20a *g);
struct nvgpu_init_table_t {
nvgpu_init_func_t func;
@@ -522,6 +533,7 @@ int nvgpu_finalize_poweron(struct gk20a *g)
#ifdef CONFIG_NVGPU_DGPU
NVGPU_INIT_TABLE_ENTRY(g->ops.bios.bios_sw_init, NO_FLAG),
#endif
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_interrupt_setup, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.bus.init_hw, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.priv_ring.enable_priv_ring,
NO_FLAG),
@@ -548,7 +560,6 @@ int nvgpu_finalize_poweron(struct gk20a *g)
NVGPU_INIT_TABLE_ENTRY(g->ops.fifo.fifo_init_support, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.therm.elcg_init_idle_filters,
NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.mc.intr_enable, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_acquire_tpc_pg_lock, NO_FLAG),
#ifdef CONFIG_NVGPU_DEBUGGER