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gpu: nvgpu: reorganization of MC interrupts control
Previously, unit interrupt enabling/disabling and corresponding MC level interrupt enabling/disabling was not done at the same time. With this change, stall and nonstall interrupt for units are programmed at MC level along with individual unit interrupts. Kept access to MC interrupt registers through mc.intr_lock spinlock. For doing this separated CE and GR interrupt mask functions. mc.intr_enable is only used when there is global interrupt control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable is now removed. Removed following functions - mc_gv100_intr_enable, mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config as we can use the generic unit interrupt control function. JIRA NVGPU-4336 Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2196178 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
committed by
Alex Waterman
Alex Waterman
parent
daf5475f50
commit
a8c9c800cd
@@ -185,7 +185,24 @@ bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id);
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*/
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u32 nvgpu_engine_get_gr_id(struct gk20a *g);
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/**
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* @brief Get intr mask for the engines supported by the chip.
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* @brief Get intr mask for the GR engine supported by the chip.
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*
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* @param g[in] The GPU driver struct.
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*
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* For each of #nvgpu_fifo.num_engines, get pointer to
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* #nvgpu_engine_info. Use this to get #nvgpu_engine_info.intr_mask.
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* If #nvgpu_engine_info.engine_num type matches with
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* #NVGPU_ENGINE_GR, local intr_mask variable is logically ORed with
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* #nvgpu_engine_info.intr_mask.
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*
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* @return Interrupt mask for GR engine.
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* @retval 0 if #nvgpu_fifo.num_engines is 0.
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* @retval 0 if all of the supported engine enum types don't match with
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* #NVGPU_ENGINE_GR.
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*/
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u32 nvgpu_gr_engine_interrupt_mask(struct gk20a *g);
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/**
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* @brief Get intr mask for the CE engines supported by the chip.
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*
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* @param g [in] The GPU driver struct.
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*
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@@ -193,16 +210,18 @@ u32 nvgpu_engine_get_gr_id(struct gk20a *g);
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* #nvgpu_engine_info. Use this to get #nvgpu_engine_info.intr_mask.
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* If #nvgpu_engine_info.engine_num type matches with
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* #NVGPU_ENGINE_GRCE or #NVGPU_ENGINE_ASYNC_CE but interrupt handlers
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* are not supported, local intr_mask variable is not logically ORed with
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* are not supported or engine_enum type matches with #NVGPU_ENGINE_GR
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* , local intr_mask variable is not logically ORed with
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* #nvgpu_engine_info.intr_mask.
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*
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* @return Interrupt mask for h/w engines that support interrupt handlers.
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* @return Interrupt mask for CE engines that support interrupt handlers.
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* @retval 0 if #nvgpu_fifo.num_engines is 0.
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* @retval 0 if all of the supported engine enum types match with
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* #NVGPU_ENGINE_GRCE or #NVGPU_ENGINE_ASYNC_CE and does not
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* support interrupt handler.
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* support interrupt handler or engine enum type matches with
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* #NVGPU_ENGINE_GR.
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*/
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u32 nvgpu_engine_interrupt_mask(struct gk20a *g);
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u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g);
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/**
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* @brief Get intr mask for the h/w engine id.
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*
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@@ -184,9 +184,6 @@ struct railgate_stats {
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};
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#endif
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#define MC_INTR_UNIT_DISABLE false
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#define MC_INTR_UNIT_ENABLE true
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#define GPU_LIT_NUM_GPCS 0
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#define GPU_LIT_NUM_PES_PER_GPC 1
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#define GPU_LIT_NUM_ZCULL_BANKS 2
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@@ -72,53 +72,6 @@ struct gops_mc {
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u32 (*get_chip_details)(struct gk20a *g,
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u32 *arch, u32 *impl, u32 *rev);
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/**
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* @brief Clear the GPU device interrupts at master level.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked before powering off or finishing
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* SW quiesce of nvgpu driver.
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*
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* Steps:
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* - Write U32_MAX to the stalling interrupts enable clear register.
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* mc_intr_en_clear_r are write only registers which clear
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* the corresponding bit in INTR_EN whenever a 1 is written
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* to it.
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* - Write U32_MAX to the non-stalling interrupts enable clear register.
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*/
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void (*intr_mask)(struct gk20a *g);
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/**
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* @brief Enable the applicable GPU device interrupts at master level.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked during #nvgpu_finalize_poweron before
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* enabling the individual HW units interrupts.
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*
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* Steps:
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* - Get the engine interrupts mask for supported FIFO engines by
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* calling #nvgpu_engine_interrupt_mask.
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* - Clear the GPU device interrupts.
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* - Set the master level interrupts masks to be used for
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* enabling/disabling the interrupts at runtime in
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* #intr_stall_pause, #intr_stall_resume,
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* #intr_nonstall_pause and #intr_nonstall_resume.
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* - Initialize the stalling interrupts bitmask
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* #intr_mask_restore[#NVGPU_MC_INTR_STALLING] with various
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* units (FIFO, HUB, PRIV_RING, PBUS, LTC) OR'ing with engine
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* interrupts mask.
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* - Initialize the non-stalling interrupts bitmask
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* #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING] with FIFO
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* unit OR'ing with engine interrupts mask.
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* - Write the bitmasks to the stalling and the non-stalling interrupts
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* enable registers respectively (mc_intr_en_set_r()).
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*
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* @return 0 in case of success, < 0 in case of failure.
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*/
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int (*intr_enable)(struct gk20a *g);
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/**
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* @brief Read the the stalling interrupts status register.
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*
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@@ -135,20 +88,6 @@ struct gops_mc {
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*/
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u32 (*intr_stall)(struct gk20a *g);
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/**
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* @brief Disable/Pause the stalling interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to disable the stalling interrupts before
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* the ISR is executed.
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*
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* Steps:
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* - Write U32_MAX to the stalling interrupts enable clear register
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* (mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING)).
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*/
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void (*intr_stall_pause)(struct gk20a *g);
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/**
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* @brief Interrupt Service Routine (ISR) for handling the stalling
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* interrupts.
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@@ -184,22 +123,6 @@ struct gops_mc {
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*/
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void (*isr_stall)(struct gk20a *g);
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/**
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* @brief Enable/Resume the stalling interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to enable the stalling interrupts after
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* the ISR is executed.
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*
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* Steps:
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* - Enable the stalling interrupts as configured during #intr_enable.
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* Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the
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* stalling interrupts enable set register
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* (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
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*/
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void (*intr_stall_resume)(struct gk20a *g);
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/**
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* @brief Read the non-stalling interrupts status register.
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*
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@@ -216,20 +139,6 @@ struct gops_mc {
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*/
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u32 (*intr_nonstall)(struct gk20a *g);
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/**
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* @brief Disable/Pause the non-stalling interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to disable the non-stalling interrupts
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* before the ISR is executed.
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*
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* Steps:
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* - Write U32_MAX to the non-stalling interrupts enable clear register
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* (mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING)).
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*/
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void (*intr_nonstall_pause)(struct gk20a *g);
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/**
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* @brief Interrupt Service Routine (ISR) for handling the non-stalling
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* interrupts.
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@@ -256,23 +165,6 @@ struct gops_mc {
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*/
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u32 (*isr_nonstall)(struct gk20a *g);
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/**
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* @brief Enable/Resume the non-stalling interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to enable the non-stalling interrupts after
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* the ISR is executed.
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*
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* Steps:
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* - Enable the non-stalling interrupts as configured during
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* #intr_enable.
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* Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
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* to the non-stalling interrupts enable set register
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* (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
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*/
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void (*intr_nonstall_resume)(struct gk20a *g);
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/**
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* @brief Check if stalling or engine interrupts are pending.
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*
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@@ -345,10 +237,10 @@ struct gops_mc {
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* @param g [in] The GPU driver struct.
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* @param unit [in] Value designating the GPU HW unit/engine
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* controlled by MC. Supported values are:
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* - NVGPU_UNIT_FIFO
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* - NVGPU_UNIT_PERFMON
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* - NVGPU_UNIT_GRAPH
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* - NVGPU_UNIT_BLG
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* - #NVGPU_UNIT_FIFO
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* - #NVGPU_UNIT_PERFMON
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* - #NVGPU_UNIT_GRAPH
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* - #NVGPU_UNIT_BLG
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*
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* This function is invoked to get the reset mask of the engines for
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* resetting CE, GR, FIFO during #nvgpu_finalize_poweron.
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@@ -385,6 +277,24 @@ struct gops_mc {
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void (*intr_mask)(struct gk20a *g);
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void (*intr_enable)(struct gk20a *g);
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void (*intr_stall_unit_config)(struct gk20a *g, u32 unit,
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bool enable);
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void (*intr_nonstall_unit_config)(struct gk20a *g, u32 unit,
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bool enable);
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void (*intr_stall_pause)(struct gk20a *g);
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void (*intr_stall_resume)(struct gk20a *g);
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void (*intr_nonstall_pause)(struct gk20a *g);
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void (*intr_nonstall_resume)(struct gk20a *g);
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void (*enable)(struct gk20a *g, u32 units);
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void (*disable)(struct gk20a *g, u32 units);
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@@ -407,10 +317,6 @@ struct gops_mc {
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void (*fbpa_isr)(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_LS_PMU
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void (*intr_pmu_unit_config)(struct gk20a *g,
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bool enable);
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#endif
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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};
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@@ -153,11 +153,39 @@ enum nvgpu_unit {
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#define NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE BIT32(0)
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#define NVGPU_NONSTALL_OPS_POST_EVENTS BIT32(1)
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/** MC interrupt for Bus unit. */
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#define MC_INTR_UNIT_BUS 0
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/** MC interrupt for PRIV_RING unit. */
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#define MC_INTR_UNIT_PRIV_RING 1
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/** MC interrupt for FIFO unit. */
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#define MC_INTR_UNIT_FIFO 2
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/** MC interrupt for LTC unit. */
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#define MC_INTR_UNIT_LTC 3
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/** MC interrupt for HUB unit. */
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#define MC_INTR_UNIT_HUB 4
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/** MC interrupt for GR unit. */
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#define MC_INTR_UNIT_GR 5
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/** MC interrupt for PMU unit. */
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#define MC_INTR_UNIT_PMU 6
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/** MC interrupt for CE unit. */
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#define MC_INTR_UNIT_CE 7
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/** MC interrupt for NVLINK unit. */
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#define MC_INTR_UNIT_NVLINK 8
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/** MC interrupt for FBPA unit. */
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#define MC_INTR_UNIT_FBPA 9
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/** Value to be passed to mc.intr_*_unit_config to enable the interrupt. */
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#define MC_INTR_ENABLE true
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/** Value to be passed to mc.intr_*_unit_config to disable the interrupt. */
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#define MC_INTR_DISABLE false
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/**
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* This struct holds the variables needed to manage the configuration and
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* interrupt handling of the units/engines.
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*/
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struct nvgpu_mc {
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struct nvgpu_spinlock intr_lock;
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/** Lock to access the mc_enable_r */
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struct nvgpu_spinlock enable_lock;
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@@ -246,4 +274,182 @@ struct nvgpu_mc {
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*/
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void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
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/**
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* @brief Clear the GPU device interrupts at master level.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked before powering off or finishing
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* SW quiesce of nvgpu driver.
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*
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* Steps:
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* - Acquire the spinlock g->mc.intr_lock.
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* - Write U32_MAX to the stalling interrupts enable clear register.
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* mc_intr_en_clear_r are write only registers which clear
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* the corresponding bit in INTR_EN whenever a 1 is written
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* to it.
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* - Set g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] and
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* g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] to 0.
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* - Write U32_MAX to the non-stalling interrupts enable clear register.
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* - Release the spinlock g->mc.intr_lock.
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*/
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void nvgpu_mc_intr_mask(struct gk20a *g);
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void nvgpu_mc_log_pending_intrs(struct gk20a *g);
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void nvgpu_mc_intr_enable(struct gk20a *g);
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/**
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* @brief Enable the stalling interrupts for GPU unit at the master
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* level.
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*
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* @param g [in] The GPU driver struct.
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* @param unit [in] Value designating the GPU HW unit/engine
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* controlled by MC. Supported values are:
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* - #MC_INTR_UNIT_BUS
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* - #MC_INTR_UNIT_PRIV_RING
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* - #MC_INTR_UNIT_FIFO
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* - #MC_INTR_UNIT_LTC
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* - #MC_INTR_UNIT_HUB
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* - #MC_INTR_UNIT_GR
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* - #MC_INTR_UNIT_PMU
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* - #MC_INTR_UNIT_CE
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* - #MC_INTR_UNIT_NVLINK
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* - #MC_INTR_UNIT_FBPA
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* @param enable [in] Boolean control to enable/disable the stalling
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* interrupt. Supported values are:
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* - #MC_INTR_ENABLE
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* - #MC_INTR_DISABLE
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*
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* This function is invoked during individual unit's init before
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* enabling that unit's interrupts.
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*
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* Steps:
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* - Get the interrupt bitmask for \a unit.
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* - Acquire the spinlock g->mc.intr_lock.
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* - If interrupt is to be enabled
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* - Set interrupt bitmask in
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* #intr_mask_restore[#NVGPU_MC_INTR_STALLING].
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* - Write the interrupt bitmask to the register
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* mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING).
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* - Else
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* - Clear interrupt bitmask in
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* #intr_mask_restore[#NVGPU_MC_INTR_STALLING].
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* - Write the interrupt bitmask to the register
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* mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING).
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* - Release the spinlock g->mc.intr_lock.
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*/
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void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
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/**
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* @brief Enable the non-stalling interrupts for GPU unit at the master
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* level.
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*
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* @param g [in] The GPU driver struct.
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* @param unit [in] Value designating the GPU HW unit/engine
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* controlled by MC. Supported values are:
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* - #MC_INTR_UNIT_BUS
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* - #MC_INTR_UNIT_PRIV_RING
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* - #MC_INTR_UNIT_FIFO
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* - #MC_INTR_UNIT_LTC
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* - #MC_INTR_UNIT_HUB
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* - #MC_INTR_UNIT_GR
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* - #MC_INTR_UNIT_PMU
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* - #MC_INTR_UNIT_CE
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* - #MC_INTR_UNIT_NVLINK
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* - #MC_INTR_UNIT_FBPA
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* @param enable [in] Boolean control to enable/disable the stalling
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* interrupt. Supported values are:
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* - #MC_INTR_ENABLE
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* - #MC_INTR_DISABLE
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*
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* This function is invoked during individual unit's init before
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* enabling that unit's interrupts.
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*
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* Steps:
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* - Get the interrupt bitmask for \a unit.
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* - Acquire the spinlock g->mc.intr_lock.
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* - If interrupt is to be enabled
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* - Set interrupt bitmask in
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* #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING].
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* - Write the interrupt bitmask to the register
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* mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING).
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* - Else
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* - Clear interrupt bitmask in
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* #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING].
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* - Write the interrupt bitmask to the register
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* mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING).
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* - Release the spinlock g->mc.intr_lock.
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*/
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void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
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/**
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* @brief Disable/Pause the stalling interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to disable the stalling interrupts before
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* the ISR is executed.
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*
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* Steps:
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* - Acquire the spinlock g->mc.intr_lock.
|
||||
* - Write U32_MAX to the stalling interrupts enable clear register
|
||||
* (mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING)).
|
||||
* - Release the spinlock g->mc.intr_lock.
|
||||
*/
|
||||
void nvgpu_mc_intr_stall_pause(struct gk20a *g);
|
||||
|
||||
/**
|
||||
* @brief Enable/Resume the stalling interrupts.
|
||||
*
|
||||
* @param g [in] The GPU driver struct.
|
||||
*
|
||||
* This function is invoked to enable the stalling interrupts after
|
||||
* the ISR is executed.
|
||||
*
|
||||
* Steps:
|
||||
* - Acquire the spinlock g->mc.intr_lock.
|
||||
* - Enable the stalling interrupts as configured during #intr_enable.
|
||||
* Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the
|
||||
* stalling interrupts enable set register
|
||||
* (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
|
||||
* - Release the spinlock g->mc.intr_lock.
|
||||
*/
|
||||
void nvgpu_mc_intr_stall_resume(struct gk20a *g);
|
||||
|
||||
/**
|
||||
* @brief Disable/Pause the non-stalling interrupts.
|
||||
*
|
||||
* @param g [in] The GPU driver struct.
|
||||
*
|
||||
* This function is invoked to disable the non-stalling interrupts
|
||||
* before the ISR is executed.
|
||||
*
|
||||
* Steps:
|
||||
* - Acquire the spinlock g->mc.intr_lock.
|
||||
* - Write U32_MAX to the non-stalling interrupts enable clear register
|
||||
* (mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING)).
|
||||
* - Release the spinlock g->mc.intr_lock.
|
||||
*/
|
||||
void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
|
||||
|
||||
/**
|
||||
* @brief Enable/Resume the non-stalling interrupts.
|
||||
*
|
||||
* @param g [in] The GPU driver struct.
|
||||
*
|
||||
* This function is invoked to enable the non-stalling interrupts after
|
||||
* the ISR is executed.
|
||||
*
|
||||
* Steps:
|
||||
* - Acquire the spinlock g->mc.intr_lock.
|
||||
* - Enable the non-stalling interrupts as configured during
|
||||
* #intr_enable.
|
||||
* Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
|
||||
* to the non-stalling interrupts enable set register
|
||||
* (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
|
||||
* - Release the spinlock g->mc.intr_lock.
|
||||
*/
|
||||
void nvgpu_mc_intr_nonstall_resume(struct gk20a *g);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -102,4 +102,16 @@ struct nvgpu_raw_spinlock {
|
||||
struct __nvgpu_posix_lock lock;
|
||||
};
|
||||
|
||||
static inline void nvgpu_spinlock_irqsave(struct nvgpu_spinlock *mutex,
|
||||
unsigned long flags)
|
||||
{
|
||||
nvgpu_posix_lock_acquire(&mutex->lock);
|
||||
}
|
||||
|
||||
static inline void nvgpu_spinunlock_irqrestore(struct nvgpu_spinlock *mutex,
|
||||
unsigned long flags)
|
||||
{
|
||||
nvgpu_posix_lock_release(&mutex->lock);
|
||||
}
|
||||
|
||||
#endif /* NVGPU_POSIX_LOCK_H */
|
||||
|
||||
Reference in New Issue
Block a user