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gpu: nvgpu: reorganization of MC interrupts control

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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-09-11 14:57:19 +05:30
committed by Alex Waterman
parent daf5475f50
commit a8c9c800cd
49 changed files with 752 additions and 411 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/os/linux/intr.c
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@@ -40,7 +40,7 @@ irqreturn_t nvgpu_intr_stall(struct gk20a *g)
if (unlikely(!mc_intr_0))
return IRQ_NONE;
g->ops.mc.intr_stall_pause(g);
nvgpu_mc_intr_stall_pause(g);
#ifndef CONFIG_NVGPU_RECOVERY
if (g->sw_quiesce_pending) {
return IRQ_NONE;
@@ -68,7 +68,7 @@ irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g)
hw_irq_count = nvgpu_atomic_read(&g->mc.hw_irq_stall_count);
g->ops.mc.isr_stall(g);
g->ops.mc.intr_stall_resume(g);
nvgpu_mc_intr_stall_resume(g);
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_stall_last_handled, hw_irq_count);
@@ -96,7 +96,7 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g)
if (unlikely(!non_stall_intr_val))
return IRQ_NONE;
g->ops.mc.intr_nonstall_pause(g);
nvgpu_mc_intr_nonstall_pause(g);
#ifndef CONFIG_NVGPU_RECOVERY
if (g->sw_quiesce_pending) {
return IRQ_NONE;
@@ -119,7 +119,7 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g)
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_last_handled, hw_irq_count);
g->ops.mc.intr_nonstall_resume(g);
nvgpu_mc_intr_nonstall_resume(g);
nvgpu_cond_broadcast(&g->mc.sw_irq_nonstall_last_handled_cond);