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gpu: nvgpu: Introduce priv ring HAL and define ISR

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Introduce a priv ring HAL and define ISR as the only function in it.
Introduce a gp10b version of the ISR that writes error message to
UART for every priv ring error, and leave the old chips with silent
error handling.

Bug 1846641

Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473696
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-05-01 15:31:00 -07:00
committed by mobile promotions
parent 5a4926f291
commit a8cf64019f
10 changed files with 127 additions and 7 deletions
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2
drivers/gpu/nvgpu/gk20a/hal_gk20a.c
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@@ -35,6 +35,7 @@
#include "dbg_gpu_gk20a.h"
#include "css_gr_gk20a.h"
#include "pramin_gk20a.h"
#include "priv_ring_gk20a.h"
#include <nvgpu/log.h>
#include <nvgpu/bug.h>
@@ -155,6 +156,7 @@ int gk20a_init_hal(struct gk20a *g)
gops->pmupstate = false;
gk20a_init_bus(gops);
gk20a_init_mc(gops);
gk20a_init_priv_ring(gops);
gk20a_init_ltc(gops);
gk20a_init_gr_ops(gops);
gk20a_init_fecs_trace_ops(gops);