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gpu: nvgpu: null check for fault_ch
gk20a_gr_get_channel_from_ctx() could return NULL as a result fault_ch could be null JIRA GPUT19X-7 Change-Id: I2c8f099f63f30e576ecd221e3bec25070b026ced Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1323252 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1759,8 +1759,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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bool *early_exit, bool *ignore_debugger)
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{
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int ret;
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bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
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NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ;
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bool cilp_enabled = false;
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u32 global_mask = 0, dbgr_control0, global_esr_copy;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
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@@ -1769,6 +1768,10 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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*early_exit = false;
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*ignore_debugger = false;
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if (fault_ch)
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cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
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NVGPU_COMPUTE_PREEMPTION_MODE_CILP);
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n",
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gpc, tpc, global_esr);
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