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gpu: nvgpu: avoid gr_falcon dependency outside gr

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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:

int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
			struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);

int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
			struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
		int nvgpu_gr_halt_pipe(struct gk20a *g);

HALs also moved accordingly and updated code to reflect this.

Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;

JIRA NVGPU-3168

Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-04-17 16:46:28 -07:00
committed by mobile promotions
parent 24af0d3330
commit a91535e3a3
22 changed files with 142 additions and 147 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -304,6 +304,9 @@ static const struct gpu_ops gm20b_ops = {
.log_mme_exception = NULL,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ctxsw_prog = {
.hw_get_fecs_header_size =
gm20b_ctxsw_prog_hw_get_fecs_header_size,
@@ -568,9 +571,6 @@ static const struct gpu_ops gm20b_ops = {
.submit_fecs_sideband_method_op =
gm20b_gr_falcon_submit_fecs_sideband_method_op,
.ctrl_ctxsw = gm20b_gr_falcon_ctrl_ctxsw,
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
.get_fecs_current_ctx_data =

6
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -338,6 +338,9 @@ static const struct gpu_ops gp10b_ops = {
.log_mme_exception = NULL,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {
.detect = gp10b_ecc_detect_enabled_units,
.init = gp10b_ecc_init,
@@ -633,9 +636,6 @@ static const struct gpu_ops gp10b_ops = {
.submit_fecs_sideband_method_op =
gm20b_gr_falcon_submit_fecs_sideband_method_op,
.ctrl_ctxsw = gp10b_gr_falcon_ctrl_ctxsw,
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
.get_fecs_current_ctx_data =

6
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -452,6 +452,9 @@ static const struct gpu_ops gv100_ops = {
.log_mme_exception = NULL,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ctxsw_prog = {
.hw_get_fecs_header_size =
gm20b_ctxsw_prog_hw_get_fecs_header_size,
@@ -775,9 +778,6 @@ static const struct gpu_ops gv100_ops = {
.submit_fecs_sideband_method_op =
gm20b_gr_falcon_submit_fecs_sideband_method_op,
.ctrl_ctxsw = gp10b_gr_falcon_ctrl_ctxsw,
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
.get_fecs_current_ctx_data =

6
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -427,6 +427,9 @@ static const struct gpu_ops gv11b_ops = {
gr_gv11b_ctxsw_checksum_mismatch_mailbox_val,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {
.detect = gv11b_ecc_detect_enabled_units,
.init = gv11b_ecc_init,
@@ -752,9 +755,6 @@ static const struct gpu_ops gv11b_ops = {
.submit_fecs_sideband_method_op =
gm20b_gr_falcon_submit_fecs_sideband_method_op,
.ctrl_ctxsw = gp10b_gr_falcon_ctrl_ctxsw,
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
.get_fecs_current_ctx_data =

6
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -474,6 +474,9 @@ static const struct gpu_ops tu104_ops = {
.log_mme_exception = gr_tu104_log_mme_exception,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {
.detect = NULL,
.init = tu104_ecc_init,
@@ -805,9 +808,6 @@ static const struct gpu_ops tu104_ops = {
.submit_fecs_sideband_method_op =
gm20b_gr_falcon_submit_fecs_sideband_method_op,
.ctrl_ctxsw = gp10b_gr_falcon_ctrl_ctxsw,
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
.get_fecs_current_ctx_data =