nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: gsp: created cmd for GSP to bind ctx reg

Browse Source 
Changes
- create command for GSP firmware to bind ctx register.

NVGPU-8730

Change-Id: If92bbbc0169b6466e55f3dff05828b2b649ad3de
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2815472
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vivekku
2022-11-24 14:11:10 +00:00
committed by mobile promotions
parent f853536eac
commit a92bca9772
4 changed files with 26 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_runlist.c
View File

@@ -91,6 +91,10 @@ static void gsp_handle_cmd_ack(struct gk20a *g, struct nv_flcn_msg_gsp *msg,
nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_CONTROL_INFO_SEND"); nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_CONTROL_INFO_SEND");
*command_ack = true; *command_ack = true;
break; break;
case NV_GSP_UNIT_BIND_CTX_REG:
nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_BIND_CTX_REG");
*command_ack = true;
break;
default: default:
nvgpu_err(g, "Un-handled response from GSP"); nvgpu_err(g, "Un-handled response from GSP");
*command_ack = false; *command_ack = false;

19
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c
View File

@@ -32,6 +32,7 @@
#include "ipc/gsp_seq.h" #include "ipc/gsp_seq.h"
#include "ipc/gsp_queue.h" #include "ipc/gsp_queue.h"
#include "gsp_runlist.h" #include "gsp_runlist.h"
#include "ipc/gsp_cmd.h"
static void gsp_sched_get_file_names(struct gk20a *g, struct gsp_fw *gsp_ucode) static void gsp_sched_get_file_names(struct gk20a *g, struct gsp_fw *gsp_ucode)
{ {
@@ -208,6 +209,12 @@ int nvgpu_gsp_sched_bootstrap_ns(struct gk20a *g)
goto de_init; goto de_init;
} }
status = nvgpu_gsp_sched_bind_ctx_reg(g);
if (status != 0) {
nvgpu_err(g, "gsp bind ctx register failed");
goto de_init;
}
status = nvgpu_gsp_sched_send_devices_info(g); status = nvgpu_gsp_sched_send_devices_info(g);
if (status != 0) { if (status != 0) {
nvgpu_err(g, "gsp send device info failed"); nvgpu_err(g, "gsp send device info failed");
@@ -226,3 +233,15 @@ void nvgpu_gsp_sched_isr(struct gk20a *g)
g->ops.gsp.gsp_isr(g, gsp); g->ops.gsp.gsp_isr(g, gsp);
} }
int nvgpu_gsp_sched_bind_ctx_reg(struct gk20a *g)
{
struct nv_flcn_cmd_gsp cmd = { };
int err = 0;
nvgpu_gsp_dbg(g, " ");
err = gsp_send_cmd_and_wait_for_ack(g, &cmd,
NV_GSP_UNIT_BIND_CTX_REG, 0);
return err;
}

3
drivers/gpu/nvgpu/common/gsp_scheduler/ipc/gsp_cmd.h
View File

@@ -49,7 +49,8 @@ struct gk20a;
#define NV_GSP_UNIT_QUERY_NO_OF_DOMAINS 0x0BU #define NV_GSP_UNIT_QUERY_NO_OF_DOMAINS 0x0BU
#define NV_GSP_UNIT_QUERY_ACTIVE_DOMAIN 0X0CU #define NV_GSP_UNIT_QUERY_ACTIVE_DOMAIN 0X0CU
#define NV_GSP_UNIT_CONTROL_INFO_SEND 0X0DU #define NV_GSP_UNIT_CONTROL_INFO_SEND 0X0DU
#define NV_GSP_UNIT_END 0x0EU #define NV_GSP_UNIT_BIND_CTX_REG 0X0EU
#define NV_GSP_UNIT_END 0x0FU
#define GSP_MSG_HDR_SIZE U32(sizeof(struct gsp_hdr)) #define GSP_MSG_HDR_SIZE U32(sizeof(struct gsp_hdr))
#define GSP_CMD_HDR_SIZE U32(sizeof(struct gsp_hdr)) #define GSP_CMD_HDR_SIZE U32(sizeof(struct gsp_hdr))

1
drivers/gpu/nvgpu/include/nvgpu/gsp_sched.h
View File

@@ -123,4 +123,5 @@ int nvgpu_gsp_nvs_delete_domain(struct gk20a *g, u64 nvgpu_domain_id);
int nvgpu_gsp_nvs_update_runlist(struct gk20a *g, const char *name,struct nvgpu_runlist *rl); int nvgpu_gsp_nvs_update_runlist(struct gk20a *g, const char *name,struct nvgpu_runlist *rl);
int nvgpu_gps_sched_update_runlist(struct gk20a *g, int nvgpu_gps_sched_update_runlist(struct gk20a *g,
struct nvgpu_runlist_domain *domain, struct nvgpu_runlist *rl); struct nvgpu_runlist_domain *domain, struct nvgpu_runlist *rl);
int nvgpu_gsp_sched_bind_ctx_reg(struct gk20a *g);
#endif /* GSP_SCHED_H */ #endif /* GSP_SCHED_H */