gpu: nvgpu: create gr_intr private header

Move data structs from gr_intr.h to gr_intr_priv.h

Jira NVGPU-3230

Change-Id: I471fb7511cc85fc8551311103aef17fb1a9bec2b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107719
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr_intr.c

@@ -36,7 +36,8 @@
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/fecs_trace.h>
 
-#include "common/gr/gr_priv.h"
+#include "gr_priv.h"
+#include "gr_intr_priv.h"
 
 static void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
 		u32 mailbox_value)

drivers/gpu/nvgpu/common/gr/gr_intr_priv.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INTR_PRIV_H
+#define NVGPU_GR_INTR_PRIV_H
+
+#include <nvgpu/types.h>
+
+struct channel_gk20a;
+
+struct nvgpu_gr_intr_info {
+	u32 notify;
+	u32 semaphore;
+	u32 illegal_notify;
+	u32 illegal_method;
+	u32 illegal_class;
+	u32 fecs_error;
+	u32 class_error;
+	u32 fw_method;
+	u32 exception;
+};
+
+struct nvgpu_gr_tpc_exception {
+	bool tex_exception;
+	bool sm_exception;
+	bool mpc_exception;
+};
+
+struct nvgpu_gr_isr_data {
+	u32 addr;
+	u32 data_lo;
+	u32 data_hi;
+	u32 curr_ctx;
+	struct channel_gk20a *ch;
+	u32 offset;
+	u32 sub_chan;
+	u32 class_num;
+};
+
+#endif /* NVGPU_GR_INTR_PRIV_H */
+

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c

@@ -28,6 +28,8 @@
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_intr.h>
 
+#include "common/gr/gr_intr_priv.h"
+
 #include "gr_intr_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.h

@@ -27,6 +27,7 @@
 
 struct gk20a;
 struct channel_gk20a;
+struct nvgpu_gr_isr_data;
 
 #define NVC097_SET_GO_IDLE_TIMEOUT		0x022cU
 #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE	0x02dcU

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h

@@ -27,6 +27,8 @@
 
 struct gk20a;
 struct nvgpu_gr_config;
+struct channel_gk20a;
+struct nvgpu_gr_isr_data;
 
 #define NVC397_SET_SHADER_EXCEPTIONS		0x1528U
 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 	0x1280U

drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h

@@ -25,36 +25,11 @@
 
 #include <nvgpu/types.h>
 
+struct gk20a;
 struct channel_gk20a;
-
-struct nvgpu_gr_intr_info {
-	u32 notify;
-	u32 semaphore;
-	u32 illegal_notify;
-	u32 illegal_method;
-	u32 illegal_class;
-	u32 fecs_error;
-	u32 class_error;
-	u32 fw_method;
-	u32 exception;
-};
-
-struct nvgpu_gr_tpc_exception {
-	bool tex_exception;
-	bool sm_exception;
-	bool mpc_exception;
-};
-
-struct nvgpu_gr_isr_data {
-	u32 addr;
-	u32 data_lo;
-	u32 data_hi;
-	u32 curr_ctx;
-	struct channel_gk20a *ch;
-	u32 offset;
-	u32 sub_chan;
-	u32 class_num;
-};
+struct nvgpu_gr_intr_info;
+struct nvgpu_gr_tpc_exception;
+struct nvgpu_gr_isr_data;
 
 int nvgpu_gr_intr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
 					struct nvgpu_gr_isr_data *isr_data);