gpu: nvgpu: Introduce NVGPU_DEBUGGER build flag

Introduce build flag for NVGPU_DEBUGGER. Also introduces Makefile flag
NVGPU_REDUCED and disables NVGPU_DEBUGGER when doing a reduced
build.

Make user space build enable the reduced build.

Change-Id: I84d6142811f674f2a7652e093b63ea5e93d9143e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2002190
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Kconfig

@@ -160,3 +160,10 @@ config NVGPU_SUPPORT_TURING
 	default y
 	help
 	  Support for NVIDIA Turing family of GPU
+
+config NVGPU_DEBUGGER
+	bool "Support debugger APIs"
+	depends on GK20A
+	default y
+	help
+	  Support for debugger APIs

drivers/gpu/nvgpu/Makefile

@@ -17,6 +17,10 @@ endif
 # Turn off when this is fixed upstream, if ever.
 ccflags-y += -D__NVGPU_PREVENT_UNTRUSTED_SPECULATION
 
+ifeq ($(CONFIG_NVGPU_DEBUGGER),y)
+ccflags-y += -DNVGPU_DEBUGGER
+endif
+
 obj-$(CONFIG_GK20A) := nvgpu.o
 
 # OS independent parts of nvgpu. The work to collect files here

drivers/gpu/nvgpu/Makefile.sources

@@ -117,7 +117,6 @@ srcs += common/sim.c \
 	common/io_common.c \
 	common/ecc.c \
 	common/ce2.c \
-	common/debugger.c \
 	common/vbios/bios.c \
 	common/falcon/falcon.c \
 	common/falcon/falcon_queue.c \
@@ -309,3 +308,7 @@ srcs += common/sim.c \
 	vgpu/gp10b/vgpu_mm_gp10b.c \
 	vgpu/gp10b/vgpu_gr_gp10b.c \
 	vgpu/gm20b/vgpu_gr_gm20b.c
+
+ifeq ($(NVGPU_DEBUGGER),1)
+srcs += common/debugger.c
+endif

drivers/gpu/nvgpu/Makefile.tmk

@@ -32,6 +32,7 @@ NVGPU_NEXT_SOURCE := \
 		$(NV_COMPONENT_DIR)/../../../../nvgpu-next/drivers/gpu/nvgpu
 
 NVGPU_POSIX			:= -D__NVGPU_POSIX__
+NVGPU_REDUCED			:= 1
 
 NV_COMPONENT_NAME		:= nvgpu-drv
 NV_COMPONENT_OWN_INTERFACE_DIR	:= .
@@ -59,6 +60,12 @@ NV_COMPONENT_CFLAGS            	+= \
 	-DCONFIG_PCI_MSI \
 	-DCONFIG_TEGRA_NVLINK
 
+ifeq ($(NVGPU_REDUCED), 0)
+# Enable debugger APIs for normal builds
+NVGPU_DEBUGGER                  := 1
+NV_COMPONENT_CFLAGS             += -DNVGPU_DEBUGGER
+endif
+
 _NV_TOOLCHAIN_CFLAGS            += -rdynamic -g
 
 -include $(NV_COMPONENT_DIR)/Makefile.sources

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -5477,11 +5477,13 @@ int gk20a_gr_isr(struct gk20a *g)
 				need_reset = true;
 			}
 
+#ifdef NVGPU_DEBUGGER
 			/* signal clients waiting on an event */
 			if (g->ops.gr.sm_debugger_attached(g) &&
 				post_event && (fault_ch != NULL)) {
 				g->ops.debugger.post_events(fault_ch);
 			}
+#endif
 		}
 
 		gk20a_writel(g, gr_intr_r(), gr_intr_exception_reset_f());

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -692,6 +692,7 @@ static const struct gpu_ops gm20b_ops = {
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = nvgpu_dbg_set_powergate,
@@ -702,6 +703,7 @@ static const struct gpu_ops gm20b_ops = {
 		.release_profiler_reservation =
 			nvgpu_release_profiler_reservation,
 	},
+#endif
 	.perf = {
 		.enable_membuf = gm20b_perf_enable_membuf,
 		.disable_membuf = gm20b_perf_disable_membuf,
@@ -814,7 +816,9 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->perf = gm20b_ops.perf;
 	gops->perfbuf = gm20b_ops.perfbuf;
 	gops->debug = gm20b_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = gm20b_ops.debugger;
+#endif
 	gops->bus = gm20b_ops.bus;
 	gops->ptimer = gm20b_ops.ptimer;
 #if defined(CONFIG_GK20A_CYCLE_STATS)

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -1705,12 +1705,8 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
 		bool sm_debugger_attached, struct channel_gk20a *fault_ch,
 		bool *early_exit, bool *ignore_debugger)
 {
-	int ret;
+#ifdef NVGPU_DEBUGGER
 	bool cilp_enabled = false;
-	u32 global_mask = 0, dbgr_control0, global_esr_copy;
-	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
-	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 	struct tsg_gk20a *tsg;
 
 	*early_exit = false;
@@ -1730,6 +1726,12 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
 			gpc, tpc, global_esr);
 
 	if (cilp_enabled && sm_debugger_attached) {
+		u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+		u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+		u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
+		u32 global_mask = 0, dbgr_control0, global_esr_copy;
+		int ret;
+
 		if ((global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) != 0U) {
 			gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
 					gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
@@ -1806,6 +1808,7 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
 
 		*early_exit = true;
 	}
+#endif
 	return 0;
 }
 
@@ -1886,8 +1889,10 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g,
 			goto clean_up;
 		}
 
+#ifdef NVGPU_DEBUGGER
 		/* Post events to UMD */
 		g->ops.debugger.post_events(ch);
+#endif
 
 		tsg = &g->fifo.tsg[ch->tsgid];
 

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -766,6 +766,7 @@ static const struct gpu_ops gp10b_ops = {
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = nvgpu_dbg_set_powergate,
@@ -776,6 +777,7 @@ static const struct gpu_ops gp10b_ops = {
 		.release_profiler_reservation =
 			nvgpu_release_profiler_reservation,
 	},
+#endif
 	.perf = {
 		.enable_membuf = gm20b_perf_enable_membuf,
 		.disable_membuf = gm20b_perf_disable_membuf,
@@ -885,7 +887,9 @@ int gp10b_init_hal(struct gk20a *g)
 	gops->regops = gp10b_ops.regops;
 	gops->mc = gp10b_ops.mc;
 	gops->debug = gp10b_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = gp10b_ops.debugger;
+#endif
 	gops->perf = gp10b_ops.perf;
 	gops->perfbuf = gp10b_ops.perfbuf;
 	gops->bus = gp10b_ops.bus;

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -965,6 +965,7 @@ static const struct gpu_ops gv100_ops = {
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = nvgpu_dbg_set_powergate,
@@ -975,6 +976,7 @@ static const struct gpu_ops gv100_ops = {
 		.release_profiler_reservation =
 			nvgpu_release_profiler_reservation,
 	},
+#endif
 	.perf = {
 		.enable_membuf = gv11b_perf_enable_membuf,
 		.disable_membuf = gv11b_perf_disable_membuf,
@@ -1154,7 +1156,9 @@ int gv100_init_hal(struct gk20a *g)
 	gops->regops = gv100_ops.regops;
 	gops->mc = gv100_ops.mc;
 	gops->debug = gv100_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = gv100_ops.debugger;
+#endif
 	gops->perf = gv100_ops.perf;
 	gops->perfbuf = gv100_ops.perfbuf;
 	gops->bus = gv100_ops.bus;

drivers/gpu/nvgpu/gv11b/gr_gv11b.c

@@ -2232,6 +2232,7 @@ void gr_gv11b_get_access_map(struct gk20a *g,
 	*num_entries = (int)array_size;
 }
 
+#ifdef NVGPU_DEBUGGER
 static int gr_gv11b_handle_warp_esr_error_mmu_nack(struct gk20a *g,
 	u32 gpc, u32 tpc, u32 sm,
 	u32 warp_esr_error,
@@ -2398,6 +2399,7 @@ static int gr_gv11b_handle_all_warp_esr_errors(struct gk20a *g,
 	/* return error so that recovery is triggered by gk20a_gr_isr() */
 	return -EFAULT;
 }
+#endif
 
 /* @brief pre-process work on the SM exceptions to determine if we clear them or not.
  *
@@ -2408,12 +2410,9 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 		bool sm_debugger_attached, struct channel_gk20a *fault_ch,
 		bool *early_exit, bool *ignore_debugger)
 {
+#ifdef NVGPU_DEBUGGER
 	int ret;
 	bool cilp_enabled = false;
-	u32 global_mask = 0, dbgr_control0, global_esr_copy;
-	u32 offset = gk20a_gr_gpc_offset(g, gpc) +
-			gk20a_gr_tpc_offset(g, tpc) +
-			gv11b_gr_sm_offset(g, sm);
 	u32 warp_esr_error = gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr);
 	struct tsg_gk20a *tsg;
 
@@ -2454,6 +2453,11 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 			gpc, tpc, sm, global_esr);
 
 	if (cilp_enabled && sm_debugger_attached) {
+		u32 global_mask = 0, dbgr_control0, global_esr_copy;
+		u32 offset = gk20a_gr_gpc_offset(g, gpc) +
+				gk20a_gr_tpc_offset(g, tpc) +
+				gv11b_gr_sm_offset(g, sm);
+
 		if ((global_esr &
 		     gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) != 0U) {
 			gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
@@ -2538,6 +2542,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 
 		*early_exit = true;
 	}
+#endif
 	return 0;
 }
 

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -903,6 +903,7 @@ static const struct gpu_ops gv11b_ops = {
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = nvgpu_dbg_set_powergate,
@@ -913,6 +914,7 @@ static const struct gpu_ops gv11b_ops = {
 		.release_profiler_reservation =
 			nvgpu_release_profiler_reservation,
 	},
+#endif
 	.perf = {
 		.enable_membuf = gv11b_perf_enable_membuf,
 		.disable_membuf = gv11b_perf_disable_membuf,
@@ -1020,7 +1022,9 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->regops = gv11b_ops.regops;
 	gops->mc = gv11b_ops.mc;
 	gops->debug = gv11b_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = gv11b_ops.debugger;
+#endif
 	gops->perf = gv11b_ops.perf;
 	gops->perfbuf = gv11b_ops.perfbuf;
 	gops->bus = gv11b_ops.bus;

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1341,6 +1341,7 @@ struct gpu_ops {
 		void (*show_dump)(struct gk20a *g,
 				struct gk20a_debug_output *o);
 	} debug;
+#ifdef NVGPU_DEBUGGER
 	struct {
 		void (*post_events)(struct channel_gk20a *ch);
 		int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
@@ -1355,6 +1356,7 @@ struct gpu_ops {
 				struct dbg_session_gk20a *dbg_s,
 				struct dbg_profiler_object_data *prof_obj);
 	} debugger;
+#endif
 	struct {
 		void (*enable_membuf)(struct gk20a *g, u32 size,
 			u64 buf_addr, struct nvgpu_mem *inst_block);

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -1004,6 +1004,7 @@ static const struct gpu_ops tu104_ops = {
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = nvgpu_dbg_set_powergate,
@@ -1014,6 +1015,7 @@ static const struct gpu_ops tu104_ops = {
 		.release_profiler_reservation =
 			nvgpu_release_profiler_reservation,
 	},
+#endif
 	.perf = {
 		.enable_membuf = gv11b_perf_enable_membuf,
 		.disable_membuf = gv11b_perf_disable_membuf,
@@ -1188,7 +1190,9 @@ int tu104_init_hal(struct gk20a *g)
 	gops->regops = tu104_ops.regops;
 	gops->mc = tu104_ops.mc;
 	gops->debug = tu104_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = tu104_ops.debugger;
+#endif
 	gops->perf = tu104_ops.perf;
 	gops->perfbuf = tu104_ops.perfbuf;
 	gops->bus = tu104_ops.bus;

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -581,6 +581,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.debug = {
 		.show_dump = NULL,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = vgpu_dbg_set_powergate,
@@ -591,6 +592,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.release_profiler_reservation =
 			vgpu_release_profiler_reservation,
 	},
+#endif
 	.perfbuf = {
 		.perfbuf_enable = vgpu_perfbuffer_enable,
 		.perfbuf_disable = vgpu_perfbuffer_disable,
@@ -676,7 +678,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->regops = vgpu_gp10b_ops.regops;
 	gops->mc = vgpu_gp10b_ops.mc;
 	gops->debug = vgpu_gp10b_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = vgpu_gp10b_ops.debugger;
+#endif
 	gops->perfbuf = vgpu_gp10b_ops.perfbuf;
 	gops->bus = vgpu_gp10b_ops.bus;
 	gops->ptimer = vgpu_gp10b_ops.ptimer;

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -1006,9 +1006,11 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
 		g->ops.fifo.set_error_notifier(ch,
 				NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
 		break;
+#ifdef NVGPU_DEBUGGER
 	case TEGRA_VGPU_GR_INTR_SM_EXCEPTION:
 		g->ops.debugger.post_events(ch);
 		break;
+#endif
 	default:
 		WARN_ON(1);
 		break;

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -662,6 +662,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.debug = {
 		.show_dump = NULL,
 	},
+#ifdef NVGPU_DEBUGGER
 	.debugger = {
 		.post_events = nvgpu_dbg_gpu_post_events,
 		.dbg_set_powergate = vgpu_dbg_set_powergate,
@@ -672,6 +673,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.release_profiler_reservation =
 			vgpu_release_profiler_reservation,
 	},
+#endif
 	.perfbuf = {
 		.perfbuf_enable = vgpu_perfbuffer_enable,
 		.perfbuf_disable = vgpu_perfbuffer_disable,
@@ -752,7 +754,9 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->regops = vgpu_gv11b_ops.regops;
 	gops->mc = vgpu_gv11b_ops.mc;
 	gops->debug = vgpu_gv11b_ops.debug;
+#ifdef NVGPU_DEBUGGER
 	gops->debugger = vgpu_gv11b_ops.debugger;
+#endif
 	gops->perfbuf = vgpu_gv11b_ops.perfbuf;
 	gops->bus = vgpu_gv11b_ops.bus;
 	gops->ptimer = vgpu_gv11b_ops.ptimer;