nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Fix MISRA 13.2 errors in hal.gr.intr

Browse Source 
Fix MISRA 13.2 errors in hal.gr.intr unit.
misra_c_2012_rule_13_2_voilation: In hi32_lo32_to_u64, two function
calls in the arguments for which the order of evaluation is undefined.

Jira NVGPU-3621

Change-Id: I2c0d9a4492068f13edfb6ac6309f8679d1fbcee4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134597
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-11 13:44:28 -07:00
committed by mobile promotions
parent fd2fb6dbc7
commit a9fce07d11
1 changed files with 13 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -1442,17 +1442,20 @@ static void gv11b_gr_intr_read_sm_error_state(struct gk20a *g,
u32 offset, u32 offset,
struct nvgpu_tsg_sm_error_state *sm_error_states) struct nvgpu_tsg_sm_error_state *sm_error_states)
{ {
u32 addr_hi, addr_lo;
sm_error_states->hww_global_esr = nvgpu_readl(g, nvgpu_safe_add_u32( sm_error_states->hww_global_esr = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_sm0_hww_global_esr_r(), offset)); gr_gpc0_tpc0_sm0_hww_global_esr_r(), offset));
sm_error_states->hww_warp_esr = nvgpu_readl(g, nvgpu_safe_add_u32( sm_error_states->hww_warp_esr = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_sm0_hww_warp_esr_r(), offset)); gr_gpc0_tpc0_sm0_hww_warp_esr_r(), offset));
sm_error_states->hww_warp_esr_pc = hi32_lo32_to_u64( addr_hi = nvgpu_readl(g, nvgpu_safe_add_u32(
nvgpu_readl(g, nvgpu_safe_add_u32( gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(), offset));
gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(), offset)), addr_lo = nvgpu_readl(g, nvgpu_safe_add_u32(
nvgpu_readl(g, nvgpu_safe_add_u32( gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(), offset));
gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(), offset)));
sm_error_states->hww_warp_esr_pc = hi32_lo32_to_u64(addr_hi, addr_lo);
sm_error_states->hww_global_esr_report_mask = nvgpu_readl(g, sm_error_states->hww_global_esr_report_mask = nvgpu_readl(g,
nvgpu_safe_add_u32( nvgpu_safe_add_u32(
@@ -1553,12 +1556,11 @@ u32 gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g)
u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset) u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset)
{ {
u64 hww_warp_esr_pc; u64 hww_warp_esr_pc;
u32 addr_hi = nvgpu_readl(g, nvgpu_safe_add_u32(
hww_warp_esr_pc = hi32_lo32_to_u64( gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(), offset));
nvgpu_readl(g, nvgpu_safe_add_u32( u32 addr_lo = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(), offset)), gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(), offset));
nvgpu_readl(g, nvgpu_safe_add_u32( hww_warp_esr_pc = hi32_lo32_to_u64(addr_hi, addr_lo);
gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(), offset)));
return hww_warp_esr_pc; return hww_warp_esr_pc;
} }