gpu: nvgpu: Refactor Therm unit

-Created ucode_therm_inf.h header to include all
interface struct and macros from pmuif folder
-Removed thrmpmu.c/.h files and moved all those
functions into thrm.c file
-Renamed functions into public/private format

NVGPU-4449

Change-Id: I8015679351648e94b2d8dd22548c727294b4ddcb
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286333
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-common.yaml

@@ -641,7 +641,6 @@ pmu:
                  include/nvgpu/pmu/pmuif/ctrlclk.h,
                  include/nvgpu/pmu/pmuif/ctrlclkavfs.h,
                  include/nvgpu/pmu/pmuif/ctrlpmgr.h,
-                 include/nvgpu/pmu/pmuif/ctrltherm.h,
                  include/nvgpu/pmu/pmuif/ctrlvolt.h,
                  include/nvgpu/pmu/pmuif/acr.h,
                  include/nvgpu/pmu/pmuif/ap.h,
@@ -655,7 +654,6 @@ pmu:
                  include/nvgpu/pmu/pmuif/clk.h,
                  include/nvgpu/pmu/pmuif/pmgr.h,
                  include/nvgpu/pmu/pmuif/seq.h,
-                 include/nvgpu/pmu/pmuif/thermsensor.h,
                  include/nvgpu/pmu/pmuif/volt.h,
                  include/nvgpu/pmu/pmuif/rpc.h,
                  include/nvgpu/pmu/pmuif/nvgpu_cmdif.h ]
@@ -893,12 +891,11 @@ pmu:
       owner: Abdul S
       sources: [ common/pmu/therm/thrm.c,
                  common/pmu/therm/thrm.h,
-                 common/pmu/therm/thrmchannel.c,
+                 common/pmu/therm/therm_channel.c,
-                 common/pmu/therm/thrmchannel.h,
+                 common/pmu/therm/therm_channel.h,
-                 common/pmu/therm/thrmdev.c,
+                 common/pmu/therm/therm_dev.c,
-                 common/pmu/therm/thrmdev.h,
+                 common/pmu/therm/therm_dev.h,
-                 common/pmu/therm/thrmpmu.c,
+                 common/pmu/therm/ucode_therm_inf.h,
-                 common/pmu/therm/thrmpmu.h,
                  include/nvgpu/pmu/therm.h ]
 
     volt:

drivers/gpu/nvgpu/Makefile

@@ -160,9 +160,8 @@ nvgpu-y += \
 	common/pmu/volt/volt_dev.o \
 	common/pmu/volt/volt_policy.o \
 	common/pmu/therm/thrm.o \
-	common/pmu/therm/thrmdev.o \
+	common/pmu/therm/therm_dev.o \
-	common/pmu/therm/thrmchannel.o \
+	common/pmu/therm/therm_channel.o \
-	common/pmu/therm/thrmpmu.o \
 	common/pmu/lpwr/rppg.o \
 	common/pmu/pmu_pstate.o \
 	common/pmu/pmu_rtos_init.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -473,9 +473,8 @@ srcs += \
 	common/pmu/pmgr/pwrpolicy.c \
 	common/pmu/super_surface/super_surface.c \
 	common/pmu/therm/thrm.c \
-	common/pmu/therm/thrmchannel.c \
+	common/pmu/therm/therm_channel.c \
-	common/pmu/therm/thrmdev.c \
+	common/pmu/therm/therm_dev.c \
-	common/pmu/therm/thrmpmu.c \
 	common/pmu/volt/volt_dev.c \
 	common/pmu/volt/volt_policy.c \
 	common/pmu/volt/volt_rail.c \

drivers/gpu/nvgpu/common/pmu/pmu_pstate.c

@@ -44,7 +44,7 @@
 void nvgpu_pmu_pstate_deinit(struct gk20a *g)
 {
 	pmgr_pmu_free_pmupstate(g);
-	nvgpu_therm_pmu_free_pmupstate(g, g->pmu);
+	nvgpu_pmu_therm_deinit(g, g->pmu);
 
 	if (g->pmu->perf_pmu != NULL) {
 		nvgpu_pmu_perf_deinit(g);
@@ -62,9 +62,9 @@ static int pmu_pstate_init(struct gk20a *g)
 	int err;
 	nvgpu_log_fn(g, " ");
 
-	err = nvgpu_therm_pmu_init_pmupstate(g, g->pmu);
+	err = nvgpu_pmu_therm_init(g, g->pmu);
 	if (err != 0) {
-		nvgpu_therm_pmu_free_pmupstate(g, g->pmu);
+		nvgpu_pmu_therm_deinit(g, g->pmu);
 		return err;
 	}
 
@@ -112,7 +112,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g)
 		return err;
 	}
 
-	err = nvgpu_therm_domain_sw_setup(g, g->pmu);
+	err = nvgpu_pmu_therm_sw_setup(g, g->pmu);
 	if (err != 0) {
 		goto err_therm_pmu_init_pmupstate;
 	}
@@ -141,7 +141,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g)
 err_pmgr_pmu_init_pmupstate:
 	pmgr_pmu_free_pmupstate(g);
 err_therm_pmu_init_pmupstate:
-	nvgpu_therm_pmu_free_pmupstate(g, g->pmu);
+	nvgpu_pmu_therm_deinit(g, g->pmu);
 err_perf_pmu_init_pmupstate:
 	nvgpu_pmu_perf_deinit(g);
 
@@ -168,7 +168,7 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g)
 		return err;
 	}
 
-	err = nvgpu_therm_domain_pmu_setup(g, g->pmu);
+	err = nvgpu_pmu_therm_pmu_setup(g, g->pmu);
 	if (err != 0) {
 		return err;
 	}

drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h

@@ -137,14 +137,6 @@ struct nv_pmu_super_surface {
 			struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status
 				clk_vf_point_grp_get_status;
 		} clk;
-		struct {
-			struct nv_pmu_therm_therm_channel_boardobj_grp_set
-				therm_channel_grp_set;
-			struct nv_pmu_therm_therm_device_boardobj_grp_set
-				therm_device_grp_set;
-			struct nv_pmu_therm_therm_channel_boardobj_grp_get_status
-				therm_channel_grp_get_status;
-		} therm;
 		struct {
 			struct nv_pmu_clk_clk_vf_point_boardobj_grp_set
 				clk_vf_point_grp_set;

drivers/gpu/nvgpu/common/pmu/therm/therm_channel.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,8 +29,9 @@
 #include <nvgpu/string.h>
 #include <nvgpu/pmu/therm.h>
 
-#include "thrmchannel.h"
+#include "therm_dev.h"
-#include "thrmdev.h"
+#include "therm_channel.h"
+#include "ucode_therm_inf.h"
 #include "thrm.h"
 
 static int _therm_channel_pmudatainit_device(struct gk20a *g,
@@ -204,7 +205,7 @@ static int devinit_get_therm_channel_table(struct gk20a *g,
 
 		therm_channel_data.device.therm_dev_idx = therm_channel_table_entry->param0;
 		/* Check for valid therm device index */
-		if (!nvgpu_therm_dev_idx_is_valid(g->pmu->therm_pmu,
+		if (!therm_device_idx_is_valid(g->pmu->therm_pmu,
 				therm_channel_data.device.therm_dev_idx)) {
 			continue;
 		}
@@ -358,7 +359,7 @@ static int therm_channel_boardobj_grp_get_status(struct gk20a *g)
 
 }
 
-int nvgpu_therm_channel_get_curr_temp(struct gk20a *g, u32 *temp)
+int nvgpu_pmu_therm_channel_get_curr_temp(struct gk20a *g, u32 *temp)
 {
 	struct boardobjgrp *pboardobjgrp;
 	struct boardobj *pboardobj = NULL;
@@ -384,3 +385,24 @@ int nvgpu_therm_channel_get_curr_temp(struct gk20a *g, u32 *temp)
 	}
 	return status;
 }
+
+int therm_channel_pmu_setup(struct gk20a *g)
+{
+	int status = 0;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	nvgpu_log_info(g, " ");
+
+	if (!BOARDOBJGRP_IS_EMPTY(
+			&g->pmu->therm_pmu->therm_channelobjs.super.super)) {
+		pboardobjgrp =
+			&g->pmu->therm_pmu->therm_channelobjs.super.super;
+		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+		if (status != 0) {
+			goto exit;
+		}
+	}
+
+exit:
+	return status;
+}

drivers/gpu/nvgpu/common/pmu/therm/therm_channel.h

@@ -1,7 +1,7 @@
 /*
  * general thermal device structures & definitions
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,13 +24,9 @@
 #ifndef NVGPU_THERM_THRMCHANNEL_H
 #define NVGPU_THERM_THRMCHANNEL_H
 
-#include <nvgpu/types.h>
 #include <nvgpu/boardobj.h>
-#include <nvgpu/boardobjgrp.h>
 #include <nvgpu/boardobjgrp_e32.h>
 
-struct gk20a;
-
 struct therm_channel {
 	struct boardobj super;
 	s16 scaling;
@@ -55,5 +51,6 @@ struct therm_channel_get_status {
 };
 
 int therm_channel_sw_setup(struct gk20a *g);
+int therm_channel_pmu_setup(struct gk20a *g);
 
 #endif /* NVGPU_THERM_THRMCHANNEL_H */

drivers/gpu/nvgpu/common/pmu/therm/therm_dev.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,12 +27,12 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
-#include <nvgpu/pmu/pmuif/ctrltherm.h>
 
-#include "thrmdev.h"
+#include "therm_dev.h"
+#include "ucode_therm_inf.h"
 #include "thrm.h"
 
-bool nvgpu_therm_dev_idx_is_valid(struct therm_pmupstate *therm_pmu, u8 idx)
+bool therm_device_idx_is_valid(struct therm_pmupstate *therm_pmu, u8 idx)
 {
 	return boardobjgrp_idxisvalid(
 			&(therm_pmu->therm_deviceobjs.super.super), idx);
@@ -252,3 +252,23 @@ done:
 	nvgpu_log_info(g, " done status %x", status);
 	return status;
 }
+
+int therm_device_pmu_setup(struct gk20a *g)
+{
+	int status = 0;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	nvgpu_log_info(g, " ");
+
+	if (!BOARDOBJGRP_IS_EMPTY(
+			&g->pmu->therm_pmu->therm_deviceobjs.super.super)) {
+		pboardobjgrp = &g->pmu->therm_pmu->therm_deviceobjs.super.super;
+		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+		if (status != 0) {
+			goto exit;
+		}
+	}
+
+exit:
+	return status;
+}

drivers/gpu/nvgpu/common/pmu/therm/therm_dev.h

@@ -1,7 +1,7 @@
 /*
  * general thermal device structures & definitions
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,12 +24,10 @@
 #ifndef NVGPU_THERM_THRMDEV_H
 #define NVGPU_THERM_THRMDEV_H
 
-#include <nvgpu/types.h>
 #include <nvgpu/boardobj.h>
-#include <nvgpu/boardobjgrp.h>
 #include <nvgpu/boardobjgrp_e32.h>
 
-struct gk20a;
+struct therm_pmupstate;
 
 struct therm_devices {
 	struct boardobjgrp_e32 super;
@@ -40,6 +38,7 @@ struct therm_device {
 };
 
 int therm_device_sw_setup(struct gk20a *g);
-bool nvgpu_therm_dev_idx_is_valid(struct therm_pmupstate *therm_pmu, u8 idx);
+int therm_device_pmu_setup(struct gk20a *g);
+bool therm_device_idx_is_valid(struct therm_pmupstate *therm_pmu, u8 idx);
 
 #endif /* NVGPU_THERM_THRMDEV_H */

drivers/gpu/nvgpu/common/pmu/therm/thrm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,12 +22,25 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu/therm.h>
-#include <nvgpu/clk_arb.h>
+#include <nvgpu/boardobjgrp.h>
 
 #include "thrm.h"
-#include "thrmpmu.h"
 
-int nvgpu_therm_domain_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu)
+static void therm_unit_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
+		struct nv_pmu_rpc_header *rpc)
+{
+	switch (rpc->function) {
+	case NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD:
+		nvgpu_pmu_dbg(g,
+			"reply NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD");
+		break;
+	default:
+		nvgpu_pmu_dbg(g, "reply PMU_UNIT_THERM");
+		break;
+	}
+}
+
+int nvgpu_pmu_therm_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu)
 {
 	int status;
 
@@ -47,18 +60,33 @@ int nvgpu_therm_domain_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu)
 		goto exit;
 	}
 
-	pmu->therm_rpc_handler = nvgpu_pmu_therm_rpc_handler;
+	pmu->therm_rpc_handler = therm_unit_rpc_handler;
 
 exit:
 	return status;
 }
 
-int nvgpu_therm_domain_pmu_setup(struct gk20a *g, struct nvgpu_pmu *pmu)
+int nvgpu_pmu_therm_pmu_setup(struct gk20a *g, struct nvgpu_pmu *pmu)
 {
-	return therm_send_pmgr_tables_to_pmu(g);
+	int status;
+
+	status = therm_device_pmu_setup(g);
+	if (status != 0) {
+		nvgpu_err(g, "Therm device pmu setup failed - 0x%x", status);
+		goto exit;
 	}
 
-int nvgpu_therm_pmu_init_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu)
+	status = therm_channel_pmu_setup(g);
+	if (status != 0) {
+		nvgpu_err(g,"Therm channel pmu setup failed - 0x%x", status);
+		goto exit;
+	}
+
+exit:
+	return status;
+}
+
+int nvgpu_pmu_therm_init(struct gk20a *g, struct nvgpu_pmu *pmu)
 {
 	/* If already allocated, do not re-allocate */
 	if (pmu->therm_pmu != NULL) {
@@ -73,7 +101,7 @@ int nvgpu_therm_pmu_init_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu)
 	return 0;
 }
 
-void nvgpu_therm_pmu_free_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu)
+void nvgpu_pmu_therm_deinit(struct gk20a *g, struct nvgpu_pmu *pmu)
 {
 	nvgpu_kfree(g, pmu->therm_pmu);
 	pmu->therm_pmu = NULL;

drivers/gpu/nvgpu/common/pmu/therm/thrm.h

@@ -1,7 +1,7 @@
 /*
  * general thermal table structures & definitions
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,8 +24,8 @@
 #ifndef NVGPU_THERM_THRM_H
 #define NVGPU_THERM_THRM_H
 
-#include "thrmdev.h"
+#include "therm_channel.h"
-#include "thrmchannel.h"
+#include "therm_dev.h"
 
 struct therm_pmupstate {
 	struct therm_devices therm_deviceobjs;

drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.c

@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#include <nvgpu/gk20a.h>
-#include <nvgpu/boardobjgrp.h>
-#include <nvgpu/boardobjgrp_e32.h>
-#include <nvgpu/pmu/boardobjgrp_classes.h>
-#include <nvgpu/pmu/therm.h>
-#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
-#include <nvgpu/pmu/cmd.h>
-
-#include "thrmpmu.h"
-#include "thrm.h"
-
-int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
-{
-	int status = 0;
-	struct boardobjgrp *pboardobjgrp = NULL;
-
-	if (!BOARDOBJGRP_IS_EMPTY(&g->pmu->therm_pmu->therm_deviceobjs.super.super)) {
-		pboardobjgrp = &g->pmu->therm_pmu->therm_deviceobjs.super.super;
-		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
-		if (status != 0) {
-			nvgpu_err(g,
-				"therm_send_pmgr_tables_to_pmu - therm_device failed %x",
-				status);
-			goto exit;
-		}
-	}
-
-	if (!BOARDOBJGRP_IS_EMPTY(
-			&g->pmu->therm_pmu->therm_channelobjs.super.super)) {
-		pboardobjgrp = &g->pmu->therm_pmu->therm_channelobjs.super.super;
-		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
-		if (status != 0) {
-			nvgpu_err(g,
-				"therm_send_pmgr_tables_to_pmu - therm_channel failed %x",
-				status);
-			goto exit;
-		}
-	}
-
-exit:
-	return status;
-}
-
-void nvgpu_pmu_therm_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
-		struct nv_pmu_rpc_header *rpc)
-{
-	switch (rpc->function) {
-	case NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD:
-		nvgpu_pmu_dbg(g,
-			"reply NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD");
-		break;
-	default:
-		nvgpu_pmu_dbg(g, "reply PMU_UNIT_THERM");
-		break;
-	}
-}

drivers/gpu/nvgpu/common/pmu/therm/thrmpmu.h

@@ -1,31 +0,0 @@
-/*
- * general thermal pmu control structures & definitions
- *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_THERM_THRMPMU_H
-#define NVGPU_THERM_THRMPMU_H
-
-struct gk20a;
-
-int therm_send_pmgr_tables_to_pmu(struct gk20a *g);
-
-#endif /* NVGPU_THERM_THRMPMU_H */

drivers/gpu/nvgpu/common/pmu/therm/ucode_therm_inf.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,13 +20,11 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_PMUIF_THERMSENSOR_H
+#ifndef NVGPU_PMU_THERM_INF_H
-#define NVGPU_PMUIF_THERMSENSOR_H
+#define NVGPU_PMU_THERM_INF_H
 
-#include <nvgpu/flcnif_cmn.h>
+#define CTRL_THERMAL_THERM_DEVICE_CLASS_GPU                             0x01
-
+#define CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE                         0x01
-#include "ctrltherm.h"
-#include "boardobj.h"
 
 #define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET                         0x0000000B
 #define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET                         0x00000008
@@ -122,4 +120,4 @@ union nv_pmu_therm_therm_channel_boardobj_get_status_union
 
 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(therm, therm_channel);
 
-#endif /* NVGPU_PMUIF_THERMSENSOR_H */
+#endif /* NVGPU_PMU_THERM_INF_H */

drivers/gpu/nvgpu/include/nvgpu/boardobj.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
 
 #include <nvgpu/list.h>
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
+#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
+#include <nvgpu/pmu/pmuif/boardobj.h>
 
 struct boardobj;
 struct nvgpu_list_node;

drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrltherm.h

@@ -1,33 +0,0 @@
-/*
- * Control thermal infrastructure
- *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMUIF_CTRLTHERM_H
-#define NVGPU_PMUIF_CTRLTHERM_H
-
-#include "ctrlboardobj.h"
-
-#define CTRL_THERMAL_THERM_DEVICE_CLASS_GPU                             0x01
-
-#define CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE                         0x01
-
-#endif /* NVGPU_PMUIF_CTRLTHERM_H */

drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/nvgpu_cmdif.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,7 +25,6 @@
 #include "cmn.h"
 #include "init.h"
 #include "ap.h"
-#include "thermsensor.h"
 #include "seq.h"
 
 #define PMU_UNIT_REWIND			U8(0x00)

drivers/gpu/nvgpu/include/nvgpu/pmu/therm.h

@@ -1,7 +1,7 @@
 /*
  * general thermal pmu control structures & definitions
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,18 +26,11 @@
 
 struct gk20a;
 struct nvgpu_pmu;
-struct nv_pmu_rpc_header;
-struct pmu_msg;
 
-int nvgpu_therm_domain_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
+int nvgpu_pmu_therm_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
-int nvgpu_therm_domain_pmu_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
+int nvgpu_pmu_therm_pmu_setup(struct gk20a *g, struct nvgpu_pmu *pmu);
-int nvgpu_therm_pmu_init_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu);
+int nvgpu_pmu_therm_init(struct gk20a *g, struct nvgpu_pmu *pmu);
-void nvgpu_therm_pmu_free_pmupstate(struct gk20a *g, struct nvgpu_pmu *pmu);
+void nvgpu_pmu_therm_deinit(struct gk20a *g, struct nvgpu_pmu *pmu);
-#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
+int nvgpu_pmu_therm_channel_get_curr_temp(struct gk20a *g, u32 *temp);
-int nvgpu_therm_configure_therm_alert(struct gk20a *g, struct nvgpu_pmu *pmu);
-#endif
-void nvgpu_pmu_therm_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
-				 struct nv_pmu_rpc_header *rpc);
-int nvgpu_therm_channel_get_curr_temp(struct gk20a *g, u32 *temp);
 
 #endif /* NVGPU_PMU_THREM_H */

drivers/gpu/nvgpu/os/linux/debug_therm_tu104.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -25,7 +25,7 @@ static int therm_get_internal_sensor_curr_temp(void *data, u64 *val)
 	u32 readval;
 	int err;
 
-	err = nvgpu_therm_channel_get_curr_temp(g, &readval);
+	err = nvgpu_pmu_therm_channel_get_curr_temp(g, &readval);
 	if (!err)
 		*val = readval;
 

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2011-2020, NVIDIA Corporation.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1528,7 +1528,7 @@ static int nvgpu_gpu_get_temperature(struct gk20a *g,
 	if (err)
 		return err;
 
-	err = nvgpu_therm_channel_get_curr_temp(g, &temp_f24_8);
+	err = nvgpu_pmu_therm_channel_get_curr_temp(g, &temp_f24_8);
 	if (err) {
 		return err;
 	}