video: tegra: host: commonize set ZBC color entry

Move the set_zbc_color_entry() operation to the LTC common code
as this is part of the LTC.

Change-Id: Iba41e32e273d86fcf76094440c2313a75a928326
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/366174
(cherry picked from commit 569ce1f3370532f12face62664a07d2d17a96bef)
Reviewed-on: http://git-master/r/376505
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gk20a/ltc_common.c

@@ -92,6 +92,142 @@ static void gk20a_ltc_set_max_ways_evict_last(struct gk20a *g, u32 max_ways)
 	gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_r(), mgmt_reg);
 }
 
+static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
+{
+	struct device *d = dev_from_gk20a(g);
+	DEFINE_DMA_ATTRS(attrs);
+	dma_addr_t iova;
+
+	/* max memory size (MB) to cover */
+	u32 max_size = gr->max_comptag_mem;
+	/* one tag line covers 128KB */
+	u32 max_comptag_lines = max_size << 3;
+
+	u32 hw_max_comptag_lines =
+		ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
+
+	u32 cbc_param =
+		gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
+	u32 comptags_per_cacheline =
+		ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param);
+	u32 slices_per_fbp =
+		ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(cbc_param);
+	u32 cacheline_size =
+		512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
+
+	u32 compbit_backing_size;
+
+	gk20a_dbg_fn("");
+
+	if (max_comptag_lines == 0) {
+		gr->compbit_store.size = 0;
+		return 0;
+	}
+
+	if (max_comptag_lines > hw_max_comptag_lines)
+		max_comptag_lines = hw_max_comptag_lines;
+
+	/* no hybird fb */
+	compbit_backing_size =
+		DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) *
+		cacheline_size * slices_per_fbp * gr->num_fbps;
+
+	/* aligned to 2KB * num_fbps */
+	compbit_backing_size +=
+		gr->num_fbps << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
+
+	/* must be a multiple of 64KB */
+	compbit_backing_size = roundup(compbit_backing_size, 64*1024);
+
+	max_comptag_lines =
+		(compbit_backing_size * comptags_per_cacheline) /
+		cacheline_size * slices_per_fbp * gr->num_fbps;
+
+	if (max_comptag_lines > hw_max_comptag_lines)
+		max_comptag_lines = hw_max_comptag_lines;
+
+	gk20a_dbg_info("compbit backing store size : %d",
+		compbit_backing_size);
+	gk20a_dbg_info("max comptag lines : %d",
+		max_comptag_lines);
+
+	dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+	gr->compbit_store.size = compbit_backing_size;
+	gr->compbit_store.pages = dma_alloc_attrs(d, gr->compbit_store.size,
+					&iova, GFP_KERNEL, &attrs);
+	if (!gr->compbit_store.pages) {
+		gk20a_err(dev_from_gk20a(g), "failed to allocate"
+			   "backing store for compbit : size %d",
+			   compbit_backing_size);
+		return -ENOMEM;
+	}
+	gr->compbit_store.base_iova = iova;
+
+	gk20a_allocator_init(&gr->comp_tags, "comptag",
+			      1, /* start */
+			      max_comptag_lines - 1, /* length*/
+			      1); /* align */
+
+	return 0;
+}
+
+static int gk20a_ltc_clear_comptags(struct gk20a *g, u32 min, u32 max)
+{
+	struct gr_gk20a *gr = &g->gr;
+	u32 fbp, slice, ctrl1, val;
+	unsigned long end_jiffies = jiffies +
+		msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
+	u32 delay = GR_IDLE_CHECK_DEFAULT;
+	u32 slices_per_fbp =
+		ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(
+			gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()));
+
+	gk20a_dbg_fn("");
+
+	if (gr->compbit_store.size == 0)
+		return 0;
+
+	gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl2_r(),
+		     ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(min));
+	gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl3_r(),
+		     ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(max));
+	gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl1_r(),
+		     gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) |
+		     ltc_ltcs_ltss_cbc_ctrl1_clear_active_f());
+
+	for (fbp = 0; fbp < gr->num_fbps; fbp++) {
+		for (slice = 0; slice < slices_per_fbp; slice++) {
+
+			delay = GR_IDLE_CHECK_DEFAULT;
+
+			ctrl1 = ltc_ltc0_lts0_cbc_ctrl1_r() +
+				fbp * proj_ltc_stride_v() +
+				slice * proj_lts_stride_v();
+
+			do {
+				val = gk20a_readl(g, ctrl1);
+				if (ltc_ltcs_ltss_cbc_ctrl1_clear_v(val) !=
+				    ltc_ltcs_ltss_cbc_ctrl1_clear_active_v())
+					break;
+
+				usleep_range(delay, delay * 2);
+				delay = min_t(u32, delay << 1,
+					GR_IDLE_CHECK_MAX);
+
+			} while (time_before(jiffies, end_jiffies) ||
+					!tegra_platform_is_silicon());
+
+			if (!time_before(jiffies, end_jiffies)) {
+				gk20a_err(dev_from_gk20a(g),
+					   "comp tag clear timeout\n");
+				return -EBUSY;
+			}
+		}
+	}
+
+	return 0;
+}
+
 /*
  * Sets the ZBC color for the passed index.
  */
@@ -342,5 +478,3 @@ static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
 			    "g_elpg_flush too many retries");
 
 }
-=======
->>>>>>> 7294a959b260... video: tegra: host: comptag init and clear