diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c index 93fa547f0..d015d631b 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c @@ -307,7 +307,7 @@ static void channel_sync_syncpt_set_safe_state(struct nvgpu_channel_sync *s) nvgpu_nvhost_syncpt_set_safe_state(sp->nvhost_dev, sp->id); } -static int channel_sync_syncpt_get_id(struct nvgpu_channel_sync_syncpt *sp) +static u32 channel_sync_syncpt_get_id(struct nvgpu_channel_sync_syncpt *sp) { return sp->id; } @@ -330,7 +330,7 @@ static void channel_sync_syncpt_destroy(struct nvgpu_channel_sync *s) nvgpu_kfree(sp->c->g, sp); } -int nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s) +u32 nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s) { return channel_sync_syncpt_get_id(s); } diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c index 761e7b91f..44c0d4b42 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c @@ -199,7 +199,7 @@ void gk20a_init_fence(struct gk20a_fence *f, return; } f->ops = ops; - f->syncpt_id = -1; + f->syncpt_id = FIFO_INVAL_SYNCPT_ID; f->semaphore = NULL; f->os_fence = os_fence; } diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index e9607cf74..be12c5935 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -44,6 +44,7 @@ struct tsg_gk20a; #define FIFO_INVAL_CHANNEL_ID (~U32(0U)) #define FIFO_INVAL_TSG_ID (~U32(0U)) #define FIFO_INVAL_RUNLIST_ID (~U32(0U)) +#define FIFO_INVAL_SYNCPT_ID (~U32(0U)) #define ID_TYPE_CHANNEL 0U #define ID_TYPE_TSG 1U diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index b6a75207b..b2edbd8b5 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -157,9 +157,10 @@ int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) if (c->sync != NULL) { sync_syncpt = nvgpu_channel_sync_to_syncpt(c->sync); if (sync_syncpt != NULL) { - new_syncpt = nvgpu_channel_sync_get_syncpt_id(sync_syncpt); + new_syncpt = + nvgpu_channel_sync_get_syncpt_id(sync_syncpt); } else { - new_syncpt = -EINVAL; + new_syncpt = FIFO_INVAL_SYNCPT_ID; } } if ((new_syncpt != 0U) && (new_syncpt != old_syncpt)) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h index 1c2715a45..eaa7fb6f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h @@ -2,7 +2,7 @@ * * Nvgpu Channel Synchronization Abstraction (Syncpoints) * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,7 +38,7 @@ struct nvgpu_channel_sync_syncpt; /* * Returns the sync point id or negative number if no syncpt */ -int nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s); +u32 nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s); /* * Returns the sync point address of sync point or 0 if not supported @@ -69,10 +69,10 @@ nvgpu_channel_sync_syncpt_create(struct channel_gk20a *c, #else -static inline int nvgpu_channel_sync_get_syncpt_id( +static inline u32 nvgpu_channel_sync_get_syncpt_id( struct nvgpu_channel_sync_syncpt *s) { - return -EINVAL; + return FIFO_INVAL_SYNCPT_ID; } static inline u64 nvgpu_channel_sync_get_syncpt_address( struct nvgpu_channel_sync_syncpt *s) diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 60841b9a5..09e9e3496 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2011-2019, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -443,7 +443,7 @@ static int gk20a_ctrl_prepare_compressible_read( args->fence.syncpt_value = fence_out->syncpt_value; } else { - args->fence.syncpt_id = -1; + args->fence.syncpt_id = FIFO_INVAL_SYNCPT_ID; args->fence.syncpt_value = 0; } }