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gpu: nvgpu: create common sim reg accessors
sim reg accessors is common after it moved to use os abstract layer reg accessors. Bug 2999617 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: I1c0ff7ca1724cde09dd845c077763709ea2ef915 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517383 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,4 +1,4 @@
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# Copyright (c) 2019-2020, NVIDIA CORPORATION. All Rights Reserved.
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# Copyright (c) 2019-2021, NVIDIA CORPORATION. All Rights Reserved.
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#
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#
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# POSIX elements and units in nvgpu.
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# POSIX elements and units in nvgpu.
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#
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#
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@@ -29,7 +29,6 @@ all:
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os/posix/posix-io.c,
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os/posix/posix-io.c,
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os/posix/posix-nvhost.c,
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os/posix/posix-nvhost.c,
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os/posix/posix-nvlink.c,
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os/posix/posix-nvlink.c,
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os/posix/posix-sim.c,
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os/posix/posix-vgpu.c,
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os/posix/posix-vgpu.c,
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os/posix/posix-vidmem.c,
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os/posix/posix-vidmem.c,
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os/posix/fecs_trace_posix.c,
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os/posix/fecs_trace_posix.c,
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@@ -64,10 +64,6 @@ ifeq ($(CONFIG_NVGPU_LOGGING),1)
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srcs += os/posix/log.c
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srcs += os/posix/log.c
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endif
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endif
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ifeq ($(CONFIG_NVGPU_SIM),1)
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srcs += os/posix/posix-sim.c
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endif
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ifeq ($(CONFIG_NVGPU_DGPU),1)
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ifeq ($(CONFIG_NVGPU_DGPU),1)
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srcs += os/posix/posix-vidmem.c
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srcs += os/posix/posix-vidmem.c
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endif
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endif
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -31,6 +31,16 @@
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#include <nvgpu/bug.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/string.h>
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#include <nvgpu/string.h>
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void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v)
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{
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nvgpu_os_writel(v, sim->regs + r);
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}
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u32 sim_readl(struct sim_nvgpu *sim, u32 r)
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{
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return nvgpu_os_readl(sim->regs + r);
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}
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int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
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int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
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{
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{
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int err = 0;
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int err = 0;
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@@ -2,7 +2,7 @@
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*
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*
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* nvgpu sim support
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* nvgpu sim support
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*
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -25,7 +25,6 @@ struct platform_device;
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struct sim_nvgpu_linux {
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struct sim_nvgpu_linux {
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struct sim_nvgpu sim;
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struct sim_nvgpu sim;
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struct resource *reg_mem;
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struct resource *reg_mem;
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void __iomem *regs;
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void (*remove_support_linux)(struct gk20a *g);
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void (*remove_support_linux)(struct gk20a *g);
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};
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};
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@@ -44,6 +44,7 @@
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struct sim_nvgpu {
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struct sim_nvgpu {
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struct gk20a *g;
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struct gk20a *g;
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uintptr_t regs;
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u32 send_ring_put;
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u32 send_ring_put;
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u32 recv_ring_get;
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u32 recv_ring_get;
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u32 recv_ring_put;
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u32 recv_ring_put;
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -32,22 +32,6 @@
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#include "os_linux.h"
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#include "os_linux.h"
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#include "module.h"
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#include "module.h"
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void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v)
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{
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struct sim_nvgpu_linux *sim_linux =
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container_of(sim, struct sim_nvgpu_linux, sim);
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writel(v, sim_linux->regs + r);
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}
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u32 sim_readl(struct sim_nvgpu *sim, u32 r)
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{
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struct sim_nvgpu_linux *sim_linux =
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container_of(sim, struct sim_nvgpu_linux, sim);
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return readl(sim_linux->regs + r);
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}
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void nvgpu_remove_sim_support_linux(struct gk20a *g)
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void nvgpu_remove_sim_support_linux(struct gk20a *g)
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{
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{
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struct sim_nvgpu_linux *sim_linux;
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struct sim_nvgpu_linux *sim_linux;
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@@ -56,10 +40,10 @@ void nvgpu_remove_sim_support_linux(struct gk20a *g)
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return;
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return;
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sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
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sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
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if (sim_linux->regs) {
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if (g->sim->regs) {
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sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
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sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
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iounmap(sim_linux->regs);
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iounmap((void __iomem *)g->sim->regs);
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sim_linux->regs = NULL;
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g->sim->regs = 0U;
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}
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}
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nvgpu_kfree(g, sim_linux);
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nvgpu_kfree(g, sim_linux);
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g->sim = NULL;
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g->sim = NULL;
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@@ -69,6 +53,7 @@ int nvgpu_init_sim_support_linux(struct gk20a *g,
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struct platform_device *dev)
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struct platform_device *dev)
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{
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{
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struct sim_nvgpu_linux *sim_linux;
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struct sim_nvgpu_linux *sim_linux;
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void __iomem *addr;
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int err = -ENOMEM;
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int err = -ENOMEM;
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if (!nvgpu_platform_is_simulation(g))
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if (!nvgpu_platform_is_simulation(g))
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@@ -79,14 +64,15 @@ int nvgpu_init_sim_support_linux(struct gk20a *g,
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return err;
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return err;
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g->sim = &sim_linux->sim;
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g->sim = &sim_linux->sim;
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g->sim->g = g;
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g->sim->g = g;
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sim_linux->regs = nvgpu_devm_ioremap_resource(dev,
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addr = nvgpu_devm_ioremap_resource(dev,
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GK20A_SIM_IORESOURCE_MEM,
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GK20A_SIM_IORESOURCE_MEM,
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&sim_linux->reg_mem);
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NULL);
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if (IS_ERR(sim_linux->regs)) {
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if (IS_ERR(addr)) {
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nvgpu_err(g, "failed to remap gk20a sim regs");
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nvgpu_err(g, "failed to remap gk20a sim regs");
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err = PTR_ERR(sim_linux->regs);
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err = PTR_ERR(addr);
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goto fail;
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goto fail;
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}
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}
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g->sim->regs = (uintptr_t)addr;
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sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux;
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sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux;
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return 0;
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return 0;
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@@ -65,9 +65,9 @@ void nvgpu_remove_sim_support_linux_pci(struct gk20a *g)
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}
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}
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sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
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sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
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if (sim_linux->regs) {
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if (g->sim->regs) {
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sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
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sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
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sim_linux->regs = NULL;
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g->sim->regs = 0U;
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}
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}
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nvgpu_kfree(g, sim_linux);
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nvgpu_kfree(g, sim_linux);
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g->sim = NULL;
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g->sim = NULL;
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@@ -90,7 +90,7 @@ int nvgpu_init_sim_support_linux_pci(struct gk20a *g)
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return err;
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return err;
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g->sim = &sim_linux->sim;
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g->sim = &sim_linux->sim;
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g->sim->g = g;
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g->sim->g = g;
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sim_linux->regs = (void __iomem *)g->regs + sim_r();
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g->sim->regs = g->regs + sim_r();
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sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux_pci;
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sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux_pci;
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return 0;
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return 0;
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@@ -1,35 +0,0 @@
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/sim.h>
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#include <nvgpu/bug.h>
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void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v)
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{
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BUG();
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}
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u32 sim_readl(struct sim_nvgpu *sim, u32 r)
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{
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BUG();
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return 0;
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}
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