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gpu: nvgpu: Add CDE bits in FECS header

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In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/804625
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
sujeet baranwal
2015-09-28 15:26:23 -07:00
committed by Terje Bergstrom
parent 39e8bff2fc
commit ab93322b25
7 changed files with 31 additions and 1 deletions
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3
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -1632,6 +1632,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
if (!ctx_ptr)
return -ENOMEM;
if (g->ops.gr.enable_cde_in_fecs && c->cde)
g->ops.gr.enable_cde_in_fecs(ctx_ptr);
for (i = 0; i < gr->ctx_vars.golden_image_size / 4; i++)
gk20a_mem_wr32(ctx_ptr, i, gr->ctx_vars.local_golden_image[i]);