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gpu: nvgpu: add usermode submission interface HAL

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The patch adds the HAL interfaces for handling the usermode
submission, particularly allocating channel specific usermode
userd. These interfaces are currently implemented only on QNX,
and are created accordingly. As and when linux adds the
usermode submission support, we can revisit them
if any further changes are needed.

Change-Id: I790e0ebdfaedcdc5f6bb624652b1af4549b7b062
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683392
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sourab Gupta
2018-03-28 12:14:12 +05:30
committed by mobile promotions
parent 03b8768902
commit abd5f68eef
4 changed files with 58 additions and 3 deletions
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12
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -3916,11 +3916,19 @@ void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c)
int gk20a_fifo_setup_userd(struct channel_gk20a *c)
{
struct gk20a *g = c->g;
struct nvgpu_mem *mem = &g->fifo.userd;
u32 offset = c->chid * g->fifo.userd_entry_size / sizeof(u32);
struct nvgpu_mem *mem;
u32 offset;
gk20a_dbg_fn("");
if (nvgpu_mem_is_valid(&c->usermode_userd)) {
mem = &c->usermode_userd;
offset = 0;
} else {
mem = &g->fifo.userd;
offset = c->chid * g->fifo.userd_entry_size / sizeof(u32);
}
nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0);
nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0);
nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0);