From abe62f6fe05542f449aae7644d4e3f6f3f429a86 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 18 Oct 2018 19:53:32 +0530 Subject: [PATCH] gpu: nvgpu: tu10x PMU ucode update -Updated PMU version number to sync with p4 cl #:25133717 -As LS falcon's bootstrap is taken care by SEC2 RTOS so, removed ACRLIB from PMU ucode & disabled WPR init from PMU by setting ops .init_wpr_region to NULL -Adding dummy bytes to PMU supersurface member therm data structure to match with tu10x ucode supersurface change sequence offset. -PMU ucode update to enable ECC interrupt -Enable ECC interrupt in Falcon interrupt source -Enable routing of ECC interrupt to HOST. JIRA NVGPU-1150 Change-Id: Ib49f9bf811dc2a01252461c16a44869e07412005 Reviewed-on: https://git-master.nvidia.com/r/1929895 Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1957846 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h | 1 + drivers/gpu/nvgpu/tu104/hal_tu104.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 467e75750..924c810f7 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -41,7 +41,7 @@ #define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin" /* PMU F/W version */ -#define APP_VERSION_TU10X 24408680U +#define APP_VERSION_TU10X 25110168U #define APP_VERSION_GV11B 25005711U #define APP_VERSION_GV10X 24283706U #define APP_VERSION_GP10X 24076634U diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h index 5a5982c2f..093c3066b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h @@ -77,6 +77,7 @@ struct nv_pmu_super_surface { struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set; struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set; u8 therm_rsvd[0x1460]; + u8 rsvd[0xC580]; } therm; struct { struct perf_change_seq_pmu_script script_curr; diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index a9e61ff7f..6b23cd98b 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -769,7 +769,7 @@ static const struct gpu_ops tu104_ops = { gp106_get_internal_sensor_curr_temp, }, .pmu = { - .init_wpr_region = gv100_pmu_init_acr, + .init_wpr_region = NULL, .load_lsfalcon_ucode = gv100_load_falcon_ucode, .is_lazy_bootstrap = gp106_is_lazy_bootstrap, .is_priv_load = gp106_is_priv_load,