mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
gpu: nvgpu: add pbdma_timeout_register for gm20b and gp10b
Add pbdma_timeout_r register and the corresponding fields for GM20B and GP10B. Jira NVGPU-2950 Change-Id: I7441314b2244a9be5addb06b23b87c9b91571fba Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2086444 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
mobile promotions
parent
6789a862e6
commit
ac0b97b14a
@@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
|
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
|
||||||
*
|
*
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
@@ -114,6 +114,22 @@ static inline u32 pbdma_gp_put_r(u32 i)
|
|||||||
{
|
{
|
||||||
return 0x00040000U + i*8192U;
|
return 0x00040000U + i*8192U;
|
||||||
}
|
}
|
||||||
|
static inline u32 pbdma_timeout_r(u32 i)
|
||||||
|
{
|
||||||
|
return 0x0004012cU + i*8192U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout__size_1_v(void)
|
||||||
|
{
|
||||||
|
return 0x00000001U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout_period_m(void)
|
||||||
|
{
|
||||||
|
return U32(0xffffffffU) << 0U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout_period_max_f(void)
|
||||||
|
{
|
||||||
|
return 0xffffffffU;
|
||||||
|
}
|
||||||
static inline u32 pbdma_pb_fetch_r(u32 i)
|
static inline u32 pbdma_pb_fetch_r(u32 i)
|
||||||
{
|
{
|
||||||
return 0x00040054U + i*8192U;
|
return 0x00040054U + i*8192U;
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
|
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
|
||||||
*
|
*
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
@@ -114,6 +114,22 @@ static inline u32 pbdma_gp_put_r(u32 i)
|
|||||||
{
|
{
|
||||||
return 0x00040000U + i*8192U;
|
return 0x00040000U + i*8192U;
|
||||||
}
|
}
|
||||||
|
static inline u32 pbdma_timeout_r(u32 i)
|
||||||
|
{
|
||||||
|
return 0x0004012cU + i*8192U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout__size_1_v(void)
|
||||||
|
{
|
||||||
|
return 0x00000001U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout_period_m(void)
|
||||||
|
{
|
||||||
|
return U32(0xffffffffU) << 0U;
|
||||||
|
}
|
||||||
|
static inline u32 pbdma_timeout_period_max_f(void)
|
||||||
|
{
|
||||||
|
return 0xffffffffU;
|
||||||
|
}
|
||||||
static inline u32 pbdma_pb_fetch_r(u32 i)
|
static inline u32 pbdma_pb_fetch_r(u32 i)
|
||||||
{
|
{
|
||||||
return 0x00040054U + i*8192U;
|
return 0x00040054U + i*8192U;
|
||||||
|
|||||||
Reference in New Issue
Block a user