gpu: nvgpu: unit: add gr_prepare tests

Add support gr_prepare for sw and hw.
Add needed registers using nvgpu_posix_io_add_reg_space calls.

Add unit tests covering following functions
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw

Copy the falcon ucode binaries under userspace/firmware
directory
install-unit.sh modified to copy the firmware binaries
under nvgpu-unnit/firmware directory

Jira NVGPU-3582

Change-Id: If2131d2c48e828251208da86688b0594e62de82e
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184293
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/units/gr/init/Makefile

@@ -0,0 +1,33 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = nvgpu-gr-init.o
+MODULE = nvgpu-gr-init
+
+LIB_PATHS += -lnvgpu-gr
+include ../../Makefile.units
+
+lib$(MODULE).so: nvgpu-gr
+
+nvgpu-gr:
+	$(MAKE) -C ..
+

userspace/units/gr/init/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=nvgpu-gr-init
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/init/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = nvgpu-gr-init
+NVGPU_UNIT_SRCS = nvgpu-gr-init.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_COMPONENT_DIR)/.. \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/init/nvgpu-gr-init.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <stdlib.h>
+
+#include <unit/unit.h>
+#include <unit/io.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gr/gr.h>
+
+#include "common/gr/gr_priv.h"
+
+#include "../nvgpu-gr.h"
+
+struct unit_module_test nvgpu_gr_init_tests[] = {
+	UNIT_TEST(init_support, test_gr_init_support, NULL, 0),
+	UNIT_TEST(init_prepare, test_gr_init_prepare, NULL, 0),
+	UNIT_TEST(remove_support, test_gr_remove_support, NULL, 0),
+};
+
+UNIT_MODULE(nvgpu_gr_init, nvgpu_gr_init_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/gr/libnvgpu-gr.export

@@ -22,4 +22,5 @@
 
 test_gr_init_support
 test_gr_remove_support
+test_gr_init_prepare
 

userspace/units/gr/nvgpu-gr-gv11b.c

@@ -39,6 +39,7 @@
 #include "nvgpu-gr-gv11b.h"
 #include "nvgpu-gr-gv11b-regs.h"
 
+#define NV_PBB_FBHUB_REGSPACE 0x100B00
 /*
  * Mock I/O
  */
@@ -132,6 +133,56 @@ int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 		goto clean_up_pes_tpc_mask;
 	}
 
+	/*
+	 * GPCS_SWDX reg space
+	 *
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+		gr_gpcs_swdx_dss_zbc_color_r_r(0), 0xEFF) != 0) {
+		unit_err(m, "Add gpcs swdx reg space failed!\n");
+		goto clean_up_fs_space;
+	}
+
+	/*
+	 * PRI_GPCS_GCC reg space
+	 *
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+		gr_pri_gpcs_gcc_dbg_r(), 0x60) != 0) {
+		unit_err(m, "Add gpcs swdx reg space failed!\n");
+		goto clean_up_swdx_space;
+	}
+
+	/*
+	 * PRI_GPCS_TPCS reg space
+	 *
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+		gr_gpcs_tpcs_pe_vaf_r(), 0x7FF) != 0) {
+		unit_err(m, "Add gpcs swdx reg space failed!\n");
+		goto clean_up_gcc_space;
+	}
+
+	/*
+	 * PRI_GPCS_PPCS reg space
+	 *
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+		gr_gpcs_tpcs_pes_vsc_vpc_r(), 0x1FF) != 0) {
+		unit_err(m, "Add gpcs swdx reg space failed!\n");
+		goto clean_up_gcc_tpcs_space;
+	}
+
+	/*
+	 * FB partition reg space
+	 *
+	 */
+	if (nvgpu_posix_io_add_reg_space(g,
+		NV_PBB_FBHUB_REGSPACE, 0x1FF) != 0) {
+		unit_err(m, "Add gpcs swdx reg space failed!\n");
+		goto clean_up_gcc_ppcs_space;
+	}
+
 	/*
 	 * MC register mc_enable_r() is set during gr_init_prepare_hw hence
 	 * add it to reg space
@@ -139,13 +190,25 @@ int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 	if (nvgpu_posix_io_add_reg_space(g,
 					 mc_enable_r(), 0x4) != 0) {
 		unit_err(m, "Add mc enable reg space failed!\n");
-		goto clean_up_priv_ring;
+		goto clean_up_fbhub_space;
 	}
 
 	(void)nvgpu_posix_register_io(g, &gr_test_reg_callbacks);
 
 	return 0;
 
+clean_up_fbhub_space:
+	nvgpu_posix_io_delete_reg_space(g, NV_PBB_FBHUB_REGSPACE);
+clean_up_gcc_ppcs_space:
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_tpcs_pes_vsc_vpc_r());
+clean_up_gcc_tpcs_space:
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_tpcs_pe_vaf_r());
+clean_up_gcc_space:
+	nvgpu_posix_io_delete_reg_space(g, gr_pri_gpcs_gcc_dbg_r());
+clean_up_swdx_space:
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_swdx_dss_zbc_color_r_r(0));
+clean_up_fs_space:
+	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_fs_reg_space);
 clean_up_pes_tpc_mask:
 	nvgpu_posix_io_unregister_reg_space(g, &gv11b_gr_pes_tpc_mask_reg_space);
 clean_up_priv_ring:
@@ -164,6 +227,11 @@ clean_up_master:
 
 void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 {
+	nvgpu_posix_io_delete_reg_space(g, NV_PBB_FBHUB_REGSPACE);
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_tpcs_pes_vsc_vpc_r());
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_tpcs_pe_vaf_r());
+	nvgpu_posix_io_delete_reg_space(g, gr_pri_gpcs_gcc_dbg_r());
+	nvgpu_posix_io_delete_reg_space(g, gr_gpcs_swdx_dss_zbc_color_r_r(0));
 	nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
 	nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
 	nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space);

userspace/units/gr/nvgpu-gr.c

@@ -61,9 +61,31 @@ fail:
 	return UNIT_FAIL;
 }
 
+int test_gr_init_prepare(struct unit_module *m, struct gk20a *g, void *args)
+{
+	int err;
+
+	err = nvgpu_gr_prepare_sw(g);
+	if (err) {
+		goto prep_fail;
+	}
+
+	err = nvgpu_gr_enable_hw(g);
+	if (err) {
+		goto prep_fail;
+	}
+
+	return UNIT_SUCCESS;
+
+prep_fail:
+	return UNIT_FAIL;
+
+}
+
 int test_gr_remove_support(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
+	test_gr_cleanup_gv11b_reg_space(m, g);
 	nvgpu_gr_free(g);
 
 	return UNIT_SUCCESS;

userspace/units/gr/nvgpu-gr.h

@@ -39,5 +39,6 @@ int test_gr_init_support(struct unit_module *m,
 		struct gk20a *g, void *args);
 int test_gr_remove_support(struct unit_module *m,
 		struct gk20a *g, void *args);
-
+int test_gr_init_prepare(struct unit_module *m,
+		struct gk20a *g, void *args);
 #endif /* UNIT_NVGPU_GR_H */