From ad0a7e77beb5d074e9072a7936080d1696f30a97 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 4 Apr 2019 17:39:41 +0530 Subject: [PATCH] gpu: nvgpu: add common.gr.setup api to set preemptiom modes Add api nvgpu_gr_setup_set_preemption_mode() in common.gr.setup to set various preemption modes Define new hal g->ops.gr.setup.set_preemption_mode() that calls above common api Move corresponding code from gr_gp10b.c to common.gr.setup unit Jira NVGPU-1886 Change-Id: I7cb0187a4809156e5f90f39727a782b17219afa3 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2092170 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_setup.c | 78 ++++++++++++++++++ .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 2 +- .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 79 ------------------- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 3 - drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 6 +- drivers/gpu/nvgpu/include/nvgpu/gr/setup.h | 4 + drivers/gpu/nvgpu/os/linux/ioctl_channel.c | 4 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 2 +- 12 files changed, 93 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index c098a3d5b..cb315e532 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -188,3 +188,81 @@ void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, } } +int nvgpu_gr_setup_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + struct nvgpu_gr_ctx *gr_ctx; + struct gk20a *g = ch->g; + struct tsg_gk20a *tsg; + struct vm_gk20a *vm; + u32 class; + int err = 0; + + class = ch->obj_class; + if (class == 0U) { + return -EINVAL; + } + + tsg = tsg_gk20a_from_ch(ch); + if (tsg == NULL) { + return -EINVAL; + } + + vm = tsg->vm; + gr_ctx = tsg->gr_ctx; + + /* skip setting anything if both modes are already set */ + if ((graphics_preempt_mode != 0U) && + (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { + graphics_preempt_mode = 0; + } + + if ((compute_preempt_mode != 0U) && + (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { + compute_preempt_mode = 0; + } + + if ((graphics_preempt_mode == 0U) && (compute_preempt_mode == 0U)) { + return 0; + } + + nvgpu_log(g, gpu_dbg_sched, "chid=%d tsgid=%d pid=%d " + "graphics_preempt=%d compute_preempt=%d", + ch->chid, + ch->tsgid, + ch->tgid, + graphics_preempt_mode, + compute_preempt_mode); + err = nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(g, gr_ctx, vm, class, + graphics_preempt_mode, compute_preempt_mode); + if (err != 0) { + nvgpu_err(g, "set_ctxsw_preemption_mode failed"); + return err; + } + + err = gk20a_disable_channel_tsg(g, ch); + if (err != 0) { + return err; + } + + err = gk20a_fifo_preempt(g, ch); + if (err != 0) { + goto enable_ch; + } + + nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(ch->g, gr_ctx, ch->subctx); + + err = nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true); + if (err != 0) { + nvgpu_err(g, "can't map patch context"); + goto enable_ch; + } + g->ops.gr.init.commit_global_cb_manager(g, g->gr.config, gr_ctx, + true); + nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true); + +enable_ch: + gk20a_enable_channel_tsg(g, ch); + return err; +} diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 090b44d04..310d0c7f8 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -179,7 +179,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, .set_boosted_ctx = NULL, - .set_preemption_mode = vgpu_gr_set_preemption_mode, .pre_process_sm_exception = NULL, .set_bes_crop_debug3 = NULL, .set_bes_crop_debug4 = NULL, @@ -274,6 +273,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, .free_gr_ctx = vgpu_gr_free_gr_ctx, + .set_preemption_mode = vgpu_gr_set_preemption_mode, }, .zbc = { .add_color = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 2cf45ab17..c17f8e94d 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -202,7 +202,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, .set_boosted_ctx = NULL, - .set_preemption_mode = vgpu_gr_set_preemption_mode, .pre_process_sm_exception = NULL, .set_bes_crop_debug3 = NULL, .set_bes_crop_debug4 = NULL, @@ -317,6 +316,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, .free_gr_ctx = vgpu_gr_free_gr_ctx, + .set_preemption_mode = vgpu_gr_set_preemption_mode, }, .zbc = { .add_color = NULL, diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a309e0021..a401514ab 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1203,85 +1203,6 @@ enable_ch: return err; } -int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode) -{ - struct nvgpu_gr_ctx *gr_ctx; - struct gk20a *g = ch->g; - struct tsg_gk20a *tsg; - struct vm_gk20a *vm; - u32 class; - int err = 0; - - class = ch->obj_class; - if (class == 0U) { - return -EINVAL; - } - - tsg = tsg_gk20a_from_ch(ch); - if (tsg == NULL) { - return -EINVAL; - } - - vm = tsg->vm; - gr_ctx = tsg->gr_ctx; - - /* skip setting anything if both modes are already set */ - if ((graphics_preempt_mode != 0U) && - (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { - graphics_preempt_mode = 0; - } - - if ((compute_preempt_mode != 0U) && - (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { - compute_preempt_mode = 0; - } - - if ((graphics_preempt_mode == 0U) && (compute_preempt_mode == 0U)) { - return 0; - } - - nvgpu_log(g, gpu_dbg_sched, "chid=%d tsgid=%d pid=%d " - "graphics_preempt=%d compute_preempt=%d", - ch->chid, - ch->tsgid, - ch->tgid, - graphics_preempt_mode, - compute_preempt_mode); - err = nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(g, gr_ctx, vm, class, - graphics_preempt_mode, compute_preempt_mode); - if (err != 0) { - nvgpu_err(g, "set_ctxsw_preemption_mode failed"); - return err; - } - - err = gk20a_disable_channel_tsg(g, ch); - if (err != 0) { - return err; - } - - err = gk20a_fifo_preempt(g, ch); - if (err != 0) { - goto enable_ch; - } - - nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(ch->g, gr_ctx, ch->subctx); - - err = nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true); - if (err != 0) { - nvgpu_err(g, "can't map patch context"); - goto enable_ch; - } - g->ops.gr.init.commit_global_cb_manager(g, g->gr.config, gr_ctx, - true); - nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true); - -enable_ch: - gk20a_enable_channel_tsg(g, ch); - return err; -} - int gr_gp10b_get_preemption_mode_flags(struct gk20a *g, struct nvgpu_preemption_modes_rec *preemption_modes_rec) { diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index f35754b29..0852637cb 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -91,9 +91,6 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, int *ctx_resident_ch_fd); int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, bool boost); -int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); int gr_gp10b_get_preemption_mode_flags(struct gk20a *g, struct nvgpu_preemption_modes_rec *preemption_modes_rec); int gp10b_gr_fuse_override(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d1e7ad3d9..7aa5abee5 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -335,7 +335,6 @@ static const struct gpu_ops gp10b_ops = { .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, - .set_preemption_mode = gr_gp10b_set_preemption_mode, .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, .init_ecc = gp10b_ecc_init, @@ -462,6 +461,7 @@ static const struct gpu_ops gp10b_ops = { .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, + .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, }, .zbc = { .add_color = gp10b_gr_zbc_add_color, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 62234ac46..e4c1a693e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -450,7 +450,6 @@ static const struct gpu_ops gv100_ops = { .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, - .set_preemption_mode = gr_gp10b_set_preemption_mode, .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, @@ -593,6 +592,7 @@ static const struct gpu_ops gv100_ops = { .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, + .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, }, .zbc = { .add_color = gp10b_gr_zbc_add_color, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 036b10a98..fecb945eb 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -403,7 +403,6 @@ static const struct gpu_ops gv11b_ops = { .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, - .set_preemption_mode = gr_gp10b_set_preemption_mode, .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, @@ -554,6 +553,7 @@ static const struct gpu_ops gv11b_ops = { .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, + .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, }, .zbc = { .add_color = gp10b_gr_zbc_add_color, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 758b8eb36..b1ba328e6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -380,9 +380,6 @@ struct gpu_ops { int (*resume_contexts)(struct gk20a *g, struct dbg_session_gk20a *dbg_s, int *ctx_resident_ch_fd); - int (*set_preemption_mode)(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); int (*get_preemption_mode_flags)(struct gk20a *g, struct nvgpu_preemption_modes_rec *preemption_modes_rec); int (*set_ctxsw_preemption_mode)(struct gk20a *g, @@ -636,6 +633,9 @@ struct gpu_ops { void (*free_gr_ctx)(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); + int (*set_preemption_mode)(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); } setup; struct { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h index 7f40e3506..50455d8e4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h @@ -37,4 +37,8 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); +int nvgpu_gr_setup_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); + #endif /* NVGPU_GR_SETUP_H */ diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c index f5cffa3b6..31357baa0 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c @@ -986,13 +986,13 @@ static int nvgpu_ioctl_channel_set_preemption_mode(struct channel_gk20a *ch, { int err; - if (ch->g->ops.gr.set_preemption_mode) { + if (ch->g->ops.gr.setup.set_preemption_mode) { err = gk20a_busy(ch->g); if (err) { nvgpu_err(ch->g, "failed to power on, %d", err); return err; } - err = ch->g->ops.gr.set_preemption_mode(ch, + err = ch->g->ops.gr.setup.set_preemption_mode(ch, nvgpu_get_common_graphics_preempt_mode(graphics_preempt_mode), nvgpu_get_common_compute_preempt_mode(compute_preempt_mode)); gk20a_idle(ch->g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 0fa5f6799..d88b1f34c 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -469,7 +469,6 @@ static const struct gpu_ops tu104_ops = { .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, - .set_preemption_mode = gr_gp10b_set_preemption_mode, .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, @@ -619,6 +618,7 @@ static const struct gpu_ops tu104_ops = { .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, + .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, }, .zbc = { .add_color = gp10b_gr_zbc_add_color,