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gpu: nvgpu: use nvmem API to read fuses

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Replace the usage of tegra_fuse_readl with nvmem_cell_read_u32 for the
below fuse registers added as nvmem cells on v5.10+ kernels.

Older nvidia kernels do not have these tegra nvmem cell support.

1. FUSE_GCPLEX_CONFIG_FUSE_0
2. FUSE_RESERVED_CALIB0_0
3. FUSE_PDI0
4. FUSE_PDI1

bug 200633045

Change-Id: I187400720929233fcbc1970c9bbed34347b0a9a7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2670828
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2022-02-16 16:24:14 +05:30
committed by mobile promotions
parent 71eee998b1
commit ad85b60bb0
8 changed files with 195 additions and 12 deletions
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74
drivers/gpu/nvgpu/include/nvgpu/linux/nvmem.h Normal file
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@@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __NVGPU_LINUX_NVMEM_H__
#define __NVGPU_LINUX_NVMEM_H__
#ifdef CONFIG_NVGPU_NVMEM_FUSE
/**
* @file
*
* Interface for nvmem ops.
*/
struct gk20a;
#include <nvgpu/types.h>
#include <nvgpu/errno.h>
/**
* @brief - Reads calibration fuse.
*
* @param g [in] - GPU super structure.
* @param val [out] - Populated with calibration fuse value.
*
* - Provide information about the calibration fuse.
*
* @return 0 on success.
*
*/
int nvgpu_tegra_nvmem_read_reserved_calib(struct gk20a *g, u32 *val);
/**
* @brief - Reads GCPLEX_CONFIG_FUSE configuration.
*
* @param g [in] - GPU super structure.
* @param val [out] - Populated with register GCPLEX_CONFIG_FUSE value.
*
* - Provide information about the GPU complex configuration.
*
* @return 0 on success.
*
*/
int nvgpu_tegra_nvmem_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
/**
* @brief - Reads the per-device identifier fuses.
*
* @param g [in] - GPU super structure.
* @param pdi [out] - Per-device identifier
*
* The per-device identifier fuses are FUSE_PDI0 and FUSE_PDI1.
*
* @return 0 on success
*/
int nvgpu_tegra_nvmem_read_per_device_identifier(struct gk20a *g, u64 *pdi);
#endif /* CONFIG_NVGPU_NVMEM_FUSE */
#endif /* __NVGPU_LINUX_NVMEM_H__ */

22
drivers/gpu/nvgpu/include/nvgpu/linux/soc_fuse.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,13 +18,17 @@
#define NVGPU_LINUX_SOC_FUSE_H
/*
* Note: Following defines should be ideally in tegra fuse driver. They are
* defined here since nvgpu uses the tegra_fuse_readl API directly to read
* those fuses. Once nvgpu starts using nvmem API to read these fuses,
* these offsets can be defined in tegra fuse driver.
* See Bug 200633045.
* Note: Following define should be ideally in tegra fuse driver. It is
* defined here since nvgpu uses the tegra_fuse_readl API directly to
* read that fuse. See Bug 200633045.
*/
#ifndef FUSE_OPT_GPC_DISABLE_0
#define FUSE_OPT_GPC_DISABLE_0 0x188
#endif
#ifndef CONFIG_NVGPU_NVMEM_FUSE
#ifndef FUSE_GCPLEX_CONFIG_FUSE_0
#define FUSE_GCPLEX_CONFIG_FUSE_0 0x1c8
#endif
@@ -33,14 +37,12 @@
#define FUSE_RESERVED_CALIB0_0 0x204
#endif
#ifndef FUSE_OPT_GPC_DISABLE_0
#define FUSE_OPT_GPC_DISABLE_0 0x188
#endif
/* T186+ */
#if !defined(FUSE_PDI0) && !defined(FUSE_PDI1)
#define FUSE_PDI0 0x300
#define FUSE_PDI1 0x304
#endif
#endif /* !CONFIG_NVGPU_NVMEM_FUSE */
#endif /* NVGPU_LINUX_SOC_FUSE_H */