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gpu: nvgpu: move enable_hww_exceptions hal to hal.gr.intr

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Move enable_hww_exceptions hal to hal.gr.intr
Modify the calls g->ops.gr.enable_hww_exceptions to
g->ops.gr.intr.enable_hww_exceptions

JIRA NVGPU-3016

Change-Id: Ic83596acd748ca379ef81f31a7f194ab0aea1dff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082077
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-26 12:06:24 -07:00
committed by mobile promotions
parent f0a5f97ebb
commit ae0704fe7e
16 changed files with 56 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -121,7 +121,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.handle_sw_method = NULL,
.set_alpha_circular_buffer_size = NULL,
.set_circular_buffer_size = NULL,
.enable_hww_exceptions = NULL,
.is_valid_class = gr_gp10b_is_valid_class,
.is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
.is_valid_compute_class = gr_gp10b_is_valid_compute_class,

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -142,7 +142,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.handle_sw_method = NULL,
.set_alpha_circular_buffer_size = NULL,
.set_circular_buffer_size = NULL,
.enable_hww_exceptions = NULL,
.is_valid_class = gr_gv11b_is_valid_class,
.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
.is_valid_compute_class = gr_gv11b_is_valid_compute_class,

13
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1809,17 +1809,6 @@ clean_up:
return -ENOMEM;
}
void gr_gk20a_enable_hww_exceptions(struct gk20a *g)
{
/* enable exceptions */
gk20a_writel(g, gr_fe_hww_esr_r(),
gr_fe_hww_esr_en_enable_f() |
gr_fe_hww_esr_reset_active_f());
gk20a_writel(g, gr_memfmt_hww_esr_r(),
gr_memfmt_hww_esr_en_enable_f() |
gr_memfmt_hww_esr_reset_active_f());
}
void gr_gk20a_fecs_host_int_enable(struct gk20a *g)
{
gk20a_writel(g, gr_fecs_host_int_enable_r(),
@@ -1861,7 +1850,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
/* enable fecs error interrupts */
g->ops.gr.fecs_host_int_enable(g);
g->ops.gr.enable_hww_exceptions(g);
g->ops.gr.intr.enable_hww_exceptions(g);
g->ops.gr.set_hww_esr_report_mask(g);
/* enable TPC exceptions per GPC */

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -347,7 +347,6 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
u32 mode);
void gk20a_gr_set_shader_exceptions(struct gk20a *g, u32 data);
void gr_gk20a_enable_hww_exceptions(struct gk20a *g);
int gr_gk20a_load_ctxsw_ucode(struct gk20a *g);
void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g);
void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base,

3
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -246,7 +246,6 @@ static const struct gpu_ops gm20b_ops = {
.set_alpha_circular_buffer_size =
gr_gm20b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
.enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
.is_valid_class = gr_gm20b_is_valid_class,
.is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
.is_valid_compute_class = gr_gm20b_is_valid_compute_class,
@@ -470,6 +469,8 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_init_commit_global_cb_manager,
},
.intr = {
.enable_hww_exceptions =
gm20b_gr_init_enable_hww_exceptions,
.enable_interrupts = gm20b_gr_intr_enable_interrupts,
.enable_gpc_exceptions =
gm20b_gr_intr_enable_gpc_exceptions,

3
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -271,7 +271,6 @@ static const struct gpu_ops gp10b_ops = {
.set_alpha_circular_buffer_size =
gr_gp10b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
.enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
.is_valid_class = gr_gp10b_is_valid_class,
.is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
.is_valid_compute_class = gr_gp10b_is_valid_compute_class,
@@ -548,6 +547,8 @@ static const struct gpu_ops gp10b_ops = {
gp10b_gr_init_commit_global_cb_manager,
},
.intr = {
.enable_hww_exceptions =
gm20b_gr_init_enable_hww_exceptions,
.enable_interrupts = gm20b_gr_intr_enable_interrupts,
.enable_gpc_exceptions =
gm20b_gr_intr_enable_gpc_exceptions,

3
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -383,7 +383,6 @@ static const struct gpu_ops gv100_ops = {
.set_alpha_circular_buffer_size =
gr_gv11b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
.is_valid_class = gr_gv11b_is_valid_class,
.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
.is_valid_compute_class = gr_gv11b_is_valid_compute_class,
@@ -691,6 +690,8 @@ static const struct gpu_ops gv100_ops = {
gp10b_gr_init_commit_global_cb_manager,
},
.intr = {
.enable_hww_exceptions =
gv11b_gr_intr_enable_hww_exceptions,
.enable_interrupts = gm20b_gr_intr_enable_interrupts,
.enable_gpc_exceptions =
gv11b_gr_intr_enable_gpc_exceptions,

31
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -396,37 +396,6 @@ static void gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f());
}
void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
{
/* enable exceptions */
gk20a_writel(g, gr_fe_hww_esr_r(),
gr_fe_hww_esr_en_enable_f() |
gr_fe_hww_esr_reset_active_f());
gk20a_writel(g, gr_memfmt_hww_esr_r(),
gr_memfmt_hww_esr_en_enable_f() |
gr_memfmt_hww_esr_reset_active_f());
gk20a_writel(g, gr_pd_hww_esr_r(),
gr_pd_hww_esr_en_enable_f() |
gr_pd_hww_esr_reset_active_f());
gk20a_writel(g, gr_scc_hww_esr_r(),
gr_scc_hww_esr_en_enable_f() |
gr_scc_hww_esr_reset_active_f());
gk20a_writel(g, gr_ds_hww_esr_r(),
gr_ds_hww_esr_en_enabled_f() |
gr_ds_hww_esr_reset_task_f());
gk20a_writel(g, gr_ssync_hww_esr_r(),
gr_ssync_hww_esr_en_enable_f() |
gr_ssync_hww_esr_reset_active_f());
gk20a_writel(g, gr_mme_hww_esr_r(),
gr_mme_hww_esr_en_enable_f() |
gr_mme_hww_esr_reset_active_f());
/* For now leave POR values */
nvgpu_log(g, gpu_dbg_info, "gr_sked_hww_esr_en_r 0x%08x",
gk20a_readl(g, gr_sked_hww_esr_en_r()));
}
void gr_gv11b_fecs_host_int_enable(struct gk20a *g)
{
gk20a_writel(g, gr_fecs_host_int_enable_r(),

1
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -77,7 +77,6 @@ u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void);
bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num);
bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num);
void gr_gv11b_enable_hww_exceptions(struct gk20a *g);
int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch,

3
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -334,7 +334,6 @@ static const struct gpu_ops gv11b_ops = {
.set_alpha_circular_buffer_size =
gr_gv11b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
.is_valid_class = gr_gv11b_is_valid_class,
.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
.is_valid_compute_class = gr_gv11b_is_valid_compute_class,
@@ -651,6 +650,8 @@ static const struct gpu_ops gv11b_ops = {
gp10b_gr_init_commit_global_cb_manager,
},
.intr = {
.enable_hww_exceptions =
gv11b_gr_intr_enable_hww_exceptions,
.enable_interrupts = gm20b_gr_intr_enable_interrupts,
.enable_gpc_exceptions =
gv11b_gr_intr_enable_gpc_exceptions,

11
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -29,6 +29,17 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
void gm20b_gr_init_enable_hww_exceptions(struct gk20a *g)
{
/* enable exceptions */
nvgpu_writel(g, gr_fe_hww_esr_r(),
gr_fe_hww_esr_en_enable_f() |
gr_fe_hww_esr_reset_active_f());
nvgpu_writel(g, gr_memfmt_hww_esr_r(),
gr_memfmt_hww_esr_en_enable_f() |
gr_memfmt_hww_esr_reset_active_f());
}
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable)
{
if (enable) {

1
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h
View File

@@ -28,6 +28,7 @@
struct gk20a;
struct nvgpu_gr_config;
void gm20b_gr_init_enable_hww_exceptions(struct gk20a *g);
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
void gm20b_gr_intr_enable_exceptions(struct gk20a *g,
struct nvgpu_gr_config *gr_config,

31
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -29,6 +29,37 @@
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g)
{
/* enable exceptions */
nvgpu_writel(g, gr_fe_hww_esr_r(),
gr_fe_hww_esr_en_enable_f() |
gr_fe_hww_esr_reset_active_f());
nvgpu_writel(g, gr_memfmt_hww_esr_r(),
gr_memfmt_hww_esr_en_enable_f() |
gr_memfmt_hww_esr_reset_active_f());
nvgpu_writel(g, gr_pd_hww_esr_r(),
gr_pd_hww_esr_en_enable_f() |
gr_pd_hww_esr_reset_active_f());
nvgpu_writel(g, gr_scc_hww_esr_r(),
gr_scc_hww_esr_en_enable_f() |
gr_scc_hww_esr_reset_active_f());
nvgpu_writel(g, gr_ds_hww_esr_r(),
gr_ds_hww_esr_en_enabled_f() |
gr_ds_hww_esr_reset_task_f());
nvgpu_writel(g, gr_ssync_hww_esr_r(),
gr_ssync_hww_esr_en_enable_f() |
gr_ssync_hww_esr_reset_active_f());
nvgpu_writel(g, gr_mme_hww_esr_r(),
gr_mme_hww_esr_en_enable_f() |
gr_mme_hww_esr_reset_active_f());
/* For now leave POR values */
nvgpu_log(g, gpu_dbg_info, "gr_sked_hww_esr_en_r 0x%08x",
gk20a_readl(g, gr_sked_hww_esr_en_r()));
}
void gv11b_gr_intr_enable_exceptions(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
bool enable)

1
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
View File

@@ -28,6 +28,7 @@
struct gk20a;
struct nvgpu_gr_config;
void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g);
void gv11b_gr_intr_enable_exceptions(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
bool enable);

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -270,7 +270,6 @@ struct gpu_ops {
void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
void (*set_bes_crop_debug3)(struct gk20a *g, u32 data);
void (*set_bes_crop_debug4)(struct gk20a *g, u32 data);
void (*enable_hww_exceptions)(struct gk20a *g);
bool (*is_valid_class)(struct gk20a *g, u32 class_num);
bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num);
bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num);
@@ -736,6 +735,7 @@ struct gpu_ops {
} init;
struct {
void (*enable_hww_exceptions)(struct gk20a *g);
void (*enable_interrupts)(struct gk20a *g, bool enable);
void (*enable_exceptions)(struct gk20a *g,
struct nvgpu_gr_config *gr_config,

3
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -404,7 +404,6 @@ static const struct gpu_ops tu104_ops = {
.set_alpha_circular_buffer_size =
gr_gv11b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
.is_valid_class = gr_tu104_is_valid_class,
.is_valid_gfx_class = gr_tu104_is_valid_gfx_class,
.is_valid_compute_class = gr_tu104_is_valid_compute_class,
@@ -724,6 +723,8 @@ static const struct gpu_ops tu104_ops = {
gp10b_gr_init_commit_global_cb_manager,
},
.intr = {
.enable_hww_exceptions =
gv11b_gr_intr_enable_hww_exceptions,
.enable_interrupts = gm20b_gr_intr_enable_interrupts,
.enable_gpc_exceptions =
tu104_gr_intr_enable_gpc_exceptions,