diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index fbd21e618..41dcacd2f 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -979,7 +979,9 @@ static const struct gpu_ops gm20b_ops = {
 		.is_intr1_pending = gm20b_mc_is_intr1_pending,
 		.log_pending_intrs = gm20b_mc_log_pending_intrs,
 		.reset_mask = gm20b_mc_reset_mask,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.is_enabled = gm20b_mc_is_enabled,
+#endif
 		.fb_reset = gm20b_mc_fb_reset,
 		.ltc_isr = gm20b_mc_ltc_isr,
 		.is_mmu_fault_pending = gm20b_mc_is_mmu_fault_pending,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index a2ce803dc..bdb0e4a5c 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -1077,7 +1077,9 @@ static const struct gpu_ops gp10b_ops = {
 		.is_intr1_pending = mc_gp10b_is_intr1_pending,
 		.log_pending_intrs = mc_gp10b_log_pending_intrs,
 		.reset_mask = gm20b_mc_reset_mask,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.is_enabled = gm20b_mc_is_enabled,
+#endif
 		.fb_reset = gm20b_mc_fb_reset,
 		.ltc_isr = mc_gp10b_ltc_isr,
 		.is_mmu_fault_pending = gm20b_mc_is_mmu_fault_pending,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 0aa925185..dcb11785e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1292,7 +1292,9 @@ static const struct gpu_ops gv11b_ops = {
 		.is_stall_and_eng_intr_pending =
 					gv11b_mc_is_stall_and_eng_intr_pending,
 		.reset_mask = gm20b_mc_reset_mask,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.is_enabled = gm20b_mc_is_enabled,
+#endif
 		.fb_reset = NULL,
 		.ltc_isr = mc_gp10b_ltc_isr,
 		.is_mmu_fault_pending = gv11b_mc_is_mmu_fault_pending,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index ad756a927..b2b070300 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1317,7 +1317,9 @@ static const struct gpu_ops tu104_ops = {
 					gv100_mc_is_stall_and_eng_intr_pending,
 		.fbpa_isr = mc_tu104_fbpa_isr,
 		.reset_mask = gv100_mc_reset_mask,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.is_enabled = gm20b_mc_is_enabled,
+#endif
 		.fb_reset = NULL,
 		.ltc_isr = mc_tu104_ltc_isr,
 		.is_mmu_fault_pending = gv11b_mc_is_mmu_fault_pending,
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
index d56cfcea3..4c1eafff6 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
@@ -299,3 +299,12 @@ bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g)
 {
 	return g->ops.fifo.is_mmu_fault_pending(g);
 }
+
+#ifdef CONFIG_NVGPU_LS_PMU
+bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
+{
+	u32 mask = g->ops.mc.reset_mask(g, unit);
+
+	return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
+}
+#endif
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
index 457e2a927..b5c4e2a22 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
@@ -170,10 +170,3 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 
 	return mask;
 }
-
-bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
-{
-	u32 mask = g->ops.mc.reset_mask(g, unit);
-
-	return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
-}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h
index 58ed7beeb..b42d20095 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h
@@ -284,7 +284,9 @@ struct gops_mc {
 
 	void (*disable)(struct gk20a *g, u32 units);
 
+#ifdef CONFIG_NVGPU_LS_PMU
 	bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
+#endif
 
 	bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit,
 				 u32 mc_intr_1);