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gpu:nvgpu: Add gops to load pstate functions

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Add gops to choose to/not to enable
1. clk_freq_controller
2. pmgr_domain
3. lpwr_pg

Bug 200399373

Change-Id: Ie5131f9ea260f777fded8392f24815acef6cfbea
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702216
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaikundanathan S
2018-04-25 14:52:47 +05:30
committed by Tejal Kudav
parent 74ceef1230
commit ae59b322f5
4 changed files with 32 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1034,6 +1034,9 @@ struct gpu_ops {
void (*mclk_deinit)(struct gk20a *g);
int (*mclk_change)(struct gk20a *g, u16 val);
bool split_rail_support;
bool support_clk_freq_controller;
bool support_pmgr_domain;
bool support_lpwr_pg;
} clk;
struct {
u32 (*get_arbiter_clk_domains)(struct gk20a *g);

3
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -833,6 +833,9 @@ int gp106_init_hal(struct gk20a *g)
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_FALCON_ID_SEC2;
gops->clk.split_rail_support = true;
gops->clk.support_clk_freq_controller = true;
gops->clk.support_pmgr_domain = true;
gops->clk.support_lpwr_pg = true;
g->name = "gp10x";

3
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -908,6 +908,9 @@ int gv100_init_hal(struct gk20a *g)
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_FALCON_ID_SEC2;
gops->clk.split_rail_support = false;
gops->clk.support_clk_freq_controller = false;
gops->clk.support_pmgr_domain = false;
gops->clk.support_lpwr_pg = false;
g->name = "gv10x";

35
drivers/gpu/nvgpu/pstate/pstate.c
View File

@@ -96,15 +96,23 @@ int gk20a_init_pstate_support(struct gk20a *g)
if (err)
return err;
err = pmgr_domain_sw_setup(g);
if (err)
return err;
if(g->ops.clk.support_pmgr_domain) {
err = pmgr_domain_sw_setup(g);
if (err)
return err;
}
err = clk_freq_controller_sw_setup(g);
if (err)
return err;
if (g->ops.clk.support_clk_freq_controller) {
err = clk_freq_controller_sw_setup(g);
if (err)
return err;
}
err = nvgpu_lpwr_pg_setup(g);
if(g->ops.clk.support_lpwr_pg) {
err = nvgpu_lpwr_pg_setup(g);
if (err)
return err;
}
return err;
}
@@ -176,10 +184,11 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
if (err)
return err;
err = clk_freq_controller_pmu_setup(g);
if (err)
return err;
if (g->ops.clk.support_clk_freq_controller) {
err = clk_freq_controller_pmu_setup(g);
if (err)
return err;
}
err = clk_pmu_vin_load(g);
if (err)
return err;
@@ -188,7 +197,9 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
if (err)
return err;
err = pmgr_domain_pmu_setup(g);
if (g->ops.clk.support_pmgr_domain)
err = pmgr_domain_pmu_setup(g);
return err;
}