From ae6e4d0572232042bfa40d66cf4f108f9355151f Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 20 Nov 2018 13:27:45 -0800 Subject: [PATCH] gpu: nvgpu: contiguous memory for userd For a given channel, userd_iova is computed as an offset from fifo->userd address. If nvlink is enabled we need fifo->userd buffer to be physically contiguous, as nvlink bypasses IOMMU. Otherwise, it may result in loading PBDMA from an invalid location in memory. This manifests most of the time with either channel timeout (GP_PUT loaded with 0, hence no progress) or GPPTR Invalid Error (GP_PUT loaded with out of range index). Use NVGPU_DMA_FORCE_CONTIGUOUS for fifo->userd buffer, when nvlink is enabled. Bug 2422486 Change-Id: I99d585ee196534025522a1cbd74fb4e4c03df98e Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1954802 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-misra-checker Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index cda44b360..f8e579eac 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -967,7 +967,11 @@ int gk20a_init_fifo_setup_sw(struct gk20a *g) (size_t)f->num_channels, &f->userd); } else { - err = nvgpu_dma_alloc_sys(g, (size_t)f->userd_entry_size * + u32 flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ? + NVGPU_DMA_FORCE_CONTIGUOUS : 0U; + + err = nvgpu_dma_alloc_flags_sys(g, flags, + (size_t)f->userd_entry_size * (size_t)f->num_channels, &f->userd); } if (err != 0) {