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gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl

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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-04-30 17:19:51 -07:00
committed by mobile promotions
parent 5c09935297
commit af2ccb811d
16 changed files with 113 additions and 2 deletions
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16
include/uapi/linux/nvgpu.h
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@@ -168,6 +168,8 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_USERMODE_SUBMIT (1ULL << 30)
/* Reduced profile is enabled */
#define NVGPU_GPU_FLAGS_DRIVER_REDUCED_PROFILE (1ULL << 31)
/* Set MMU debug mode is available */
#define NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE (1ULL << 32)
/* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */
@@ -1448,8 +1450,20 @@ struct nvgpu_dbg_gpu_cycle_stats_snapshot_args {
#define NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT \
_IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 25, struct nvgpu_dbg_gpu_cycle_stats_snapshot_args)
/* MMU Debug Mode */
#define NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_DISABLED 0
#define NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED 1
struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args {
__u32 mode;
__u32 reserved;
};
#define NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE \
_IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 26, \
struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args)
#define NVGPU_DBG_GPU_IOCTL_LAST \
_IOC_NR(NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT)
_IOC_NR(NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE)
#define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \
sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args)