From af48120169db5f357a1a0fe08229c1af557b8c72 Mon Sep 17 00:00:00 2001 From: Ramalingam C Date: Tue, 28 Feb 2023 18:23:28 +0000 Subject: [PATCH] gpu: nvgpu: configure CWD sm id regs before ucode load GPCCS ucode is expecting the SM ID programmed in GPM and CWD registers to be in sync. So create a hal called gr.init.load_sm_id_config() for the sm_id programming for the CWD registers and invoke them before the ucode load. Initialize this hal only for the required GPUs. JIRA NVGPU-9757 Change-Id: Ib0984fd6326c37e0c2a06123041032575a23ec04 Signed-off-by: Ramalingam C Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864999 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Seema Khowala Reviewed-by: Rajesh Devaraj GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/gr/fs_state.c | 6 +++--- drivers/gpu/nvgpu/common/gr/gr.c | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 2 ++ drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h | 3 ++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index 8dad304d1..7d47a8978 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,7 +28,7 @@ #include #include -static int gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config) +int nvgpu_gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config) { int err; u32 *tpc_sm_id; @@ -130,7 +130,7 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) g->ops.gr.init.gr_load_tpc_mask(g, config); } - err = gr_load_sm_id_config(g, config); + err = nvgpu_gr_load_sm_id_config(g, config); if (err != 0) { nvgpu_err(g, "load_smid_config failed err=%d", err); } diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 4affb519b..3fb1328c8 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -818,6 +818,14 @@ static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr) } } + if (g->ops.gr.init.load_sm_id_config != NULL) { + err = g->ops.gr.init.load_sm_id_config(g, gr->config); + if (err != 0) { + nvgpu_err(g, "load_sm_id_config failed err=%d", err); + return err; + } + } + return 0; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 658a4f555..731ad1f3f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -935,6 +935,8 @@ struct gops_gr_init { int (*reset_gpcs)(struct gk20a *g); int (*sm_id_config_early)(struct gk20a *g, struct nvgpu_gr_config *config); + int (*load_sm_id_config)(struct gk20a *g, + struct nvgpu_gr_config *config); void (*set_sm_l1tag_surface_collector)(struct gk20a *g); /** @endcond */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h index 98aaa5916..996e6c800 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -53,6 +53,7 @@ struct nvgpu_gr_config; int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config); /** @cond DOXYGEN_SHOULD_SKIP_THIS */ int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config); +int nvgpu_gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config); /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif /* NVGPU_GR_FS_STATE_H */