gpu: nvgpu: gm20b: bit shift issues in hw headers

MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.

The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.

The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.

JIRA NVGPU-1054

Change-Id: I7e39bc38b620c8a521a4a75d41379b8fb107f347
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933531
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CCSR_GM20B_H
 #define NVGPU_HW_CCSR_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ccsr_channel_inst_r(u32 i)
 {
 	return 0x00800000U + i*8U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CE2_GM20B_H
 #define NVGPU_HW_CE2_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ce2_intr_status_r(void)
 {
 	return 0x00106908U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CTXSW_PROG_GM20B_H
 #define NVGPU_HW_CTXSW_PROG_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ctxsw_prog_fecs_header_v(void)
 {
 	return 0x00000100U;
@@ -114,7 +116,7 @@ static inline u32 ctxsw_prog_main_image_pm_o(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
@@ -122,7 +124,7 @@ static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
-	return 0x7U << 3U;
+	return U32(0x7U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
 {
@@ -138,7 +140,7 @@ static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v)
 }
 static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
 {
@@ -234,7 +236,7 @@ static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
 {
@@ -262,7 +264,7 @@ static inline u32 ctxsw_prog_main_image_misc_options_o(void)
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
 {
@@ -282,11 +284,11 @@ static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
 {
@@ -370,7 +372,7 @@ static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
 {
-	return 0xffU << 24U;
+	return U32(0xffU) << 24U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FALCON_GM20B_H
 #define NVGPU_HW_FALCON_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 falcon_falcon_irqsset_r(void)
 {
 	return 0x00000000U;
@@ -310,7 +312,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -318,7 +320,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 }
 static inline u32 falcon_falcon_cpuctl_stopped_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 {
@@ -326,7 +328,7 @@ static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -390,11 +392,11 @@ static inline u32 falcon_falcon_dmactl_r(void)
 }
 static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
 {
@@ -490,7 +492,7 @@ static inline u32 falcon_falcon_exterrstat_r(void)
 }
 static inline u32 falcon_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
 {
@@ -514,7 +516,7 @@ static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 falcon_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -546,7 +548,7 @@ static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 {
@@ -554,7 +556,7 @@ static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
 {
@@ -582,7 +584,7 @@ static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FB_GM20B_H
 #define NVGPU_HW_FB_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
 	return 0x00100800U;
@@ -138,7 +140,7 @@ static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
 {
@@ -162,7 +164,7 @@ static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
 }
 static inline u32 fb_mmu_debug_wr_aperture_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
 {
@@ -238,7 +240,7 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
 }
 static inline u32 fb_mmu_debug_ctrl_debug_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FIFO_GM20B_H
 #define NVGPU_HW_FIFO_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fifo_bar1_base_r(void)
 {
 	return 0x00002254U;
@@ -230,7 +232,7 @@ static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
 }
 static inline u32 fifo_intr_en_0_sched_error_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
 {
@@ -238,7 +240,7 @@ static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
 }
 static inline u32 fifo_intr_en_0_mmu_fault_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 fifo_intr_en_1_r(void)
 {
@@ -350,7 +352,7 @@ static inline u32 fifo_fb_timeout_r(void)
 }
 static inline u32 fifo_fb_timeout_period_m(void)
 {
-	return 0x3fffffffU << 0U;
+	return U32(0x3fffffffU) << 0U;
 }
 static inline u32 fifo_fb_timeout_period_max_f(void)
 {
@@ -370,7 +372,7 @@ static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
 }
 static inline u32 fifo_sched_disable_runlist_m(u32 i)
 {
-	return 0x1U << (0U + i*1U);
+	return U32(0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_sched_disable_true_v(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FLUSH_GM20B_H
 #define NVGPU_HW_FLUSH_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 flush_l2_system_invalidate_r(void)
 {
 	return 0x00070004U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FUSE_GM20B_H
 #define NVGPU_HW_FUSE_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fuse_status_opt_gpc_r(void)
 {
 	return 0x00021c1cU;
@@ -78,7 +80,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
 {
@@ -94,7 +96,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
 {
@@ -118,7 +120,7 @@ static inline u32 fuse_status_opt_fbio_data_f(u32 v)
 }
 static inline u32 fuse_status_opt_fbio_data_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 fuse_status_opt_fbio_data_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GMMU_GM20B_H
 #define NVGPU_HW_GMMU_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gmmu_pde_aperture_big_w(void)
 {
 	return 0U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GR_GM20B_H
 #define NVGPU_HW_GR_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gr_intr_r(void)
 {
 	return 0x00400100U;
@@ -166,39 +168,39 @@ static inline u32 gr_exception_r(void)
 }
 static inline u32 gr_exception_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception_gpc_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 gr_exception_memfmt_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_exception_ds_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_exception_sked_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_exception_pd_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_exception_scc_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_exception_ssync_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_exception_mme_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_exception1_r(void)
 {
@@ -218,7 +220,7 @@ static inline u32 gr_exception_en_r(void)
 }
 static inline u32 gr_exception_en_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception1_en_r(void)
 {
@@ -394,7 +396,7 @@ static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
 }
 static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
@@ -406,7 +408,7 @@ static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_sked_activity_r(void)
 {
@@ -658,11 +660,11 @@ static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_fecs_os_r(void)
 {
@@ -730,7 +732,7 @@ static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
 }
 static inline u32 gr_fecs_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
 {
@@ -794,7 +796,7 @@ static inline u32 gr_fecs_dmemc_offs_f(u32 v)
 }
 static inline u32 gr_fecs_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 gr_fecs_dmemc_offs_v(u32 r)
 {
@@ -886,7 +888,7 @@ static inline u32 gr_fecs_current_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_current_ctx_target_v(u32 r)
 {
@@ -914,7 +916,7 @@ static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
 {
@@ -1110,7 +1112,7 @@ static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
 {
@@ -1178,7 +1180,7 @@ static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
 {
@@ -1194,7 +1196,7 @@ static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_fbps_m(void)
 {
-	return 0x1fU << 16U;
+	return U32(0x1fU) << 16U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
 {
@@ -1222,7 +1224,7 @@ static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
 {
@@ -1242,7 +1244,7 @@ static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
 {
@@ -1266,7 +1268,7 @@ static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
 {
@@ -1282,7 +1284,7 @@ static inline u32 gr_fecs_new_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_new_ctx_target_v(u32 r)
 {
@@ -1310,7 +1312,7 @@ static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
 {
@@ -1330,7 +1332,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
 {
@@ -1346,7 +1348,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
 {
@@ -1378,7 +1380,7 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
 {
@@ -1666,7 +1668,7 @@ static inline u32 gr_ds_zbc_z_val_f(u32 v)
 }
 static inline u32 gr_ds_zbc_z_val_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_z_val_v(u32 r)
 {
@@ -1750,7 +1752,7 @@ static inline u32 gr_ds_hww_esr_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_reset_v(u32 r)
 {
@@ -1782,7 +1784,7 @@ static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_2_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
 {
@@ -1994,7 +1996,7 @@ static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
 {
@@ -2118,7 +2120,7 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
 {
@@ -2142,7 +2144,7 @@ static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lane_size_v_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
 {
@@ -2270,7 +2272,7 @@ static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
 {
@@ -2286,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
@@ -2310,7 +2312,7 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
 {
@@ -2334,7 +2336,7 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
 {
@@ -2342,7 +2344,7 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
@@ -2358,7 +2360,7 @@ static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
 {
@@ -2382,7 +2384,7 @@ static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_msb_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
 {
@@ -2406,7 +2408,7 @@ static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_ext_m(void)
 {
-	return 0xfffU << 0U;
+	return U32(0xfffU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
 {
@@ -2430,11 +2432,11 @@ static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpccs_imemc_r(u32 i)
 {
@@ -2510,7 +2512,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
 {
@@ -2538,7 +2540,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
 {
-	return 0x7ffU << 0U;
+	return U32(0x7ffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 {
@@ -2562,7 +2564,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
 {
@@ -2594,7 +2596,7 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
 {
@@ -2602,7 +2604,7 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
 {
@@ -2926,7 +2928,7 @@ static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
 {
-	return 0x7U << 28U;
+	return U32(0x7U) << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
 {
@@ -3254,7 +3256,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
@@ -3298,7 +3300,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
 {
@@ -3310,7 +3312,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
 {
@@ -3494,7 +3496,7 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 {
@@ -3510,7 +3512,7 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
@@ -3626,7 +3628,7 @@ static inline u32 gr_bes_crop_debug3_r(void)
 }
 static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_bes_crop_settings_r(void)
 {
@@ -3786,43 +3788,43 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
 {
-	return 0x3U << 3U;
+	return U32(0x3U) << 3U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
 {
-	return 0x3U << 5U;
+	return U32(0x3U) << 5U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {
@@ -3838,7 +3840,7 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
 }
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
 {
@@ -3886,7 +3888,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
 {
@@ -3902,7 +3904,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
 {
@@ -3914,7 +3916,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_LTC_GM20B_H
 #define NVGPU_HW_LTC_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ltc_pltcg_base_v(void)
 {
 	return 0x00140000U;
@@ -90,7 +92,7 @@ static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
 }
 static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
 {
@@ -238,7 +240,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
 {
@@ -306,15 +308,15 @@ static inline u32 ltc_ltcs_ltss_intr_r(void)
 }
 static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 ltc_ltc0_lts0_intr_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_MC_GM20B_H
 #define NVGPU_HW_MC_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 mc_boot_0_r(void)
 {
 	return 0x00000000U;
@@ -134,7 +136,7 @@ static inline u32 mc_intr_mask_1_pmu_f(u32 v)
 }
 static inline u32 mc_intr_mask_1_pmu_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 mc_intr_mask_1_pmu_v(u32 r)
 {
@@ -178,7 +180,7 @@ static inline u32 mc_enable_pmedia_f(u32 v)
 }
 static inline u32 mc_enable_pmedia_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 mc_enable_pmedia_v(u32 r)
 {
@@ -190,7 +192,7 @@ static inline u32 mc_enable_priv_ring_enabled_f(void)
 }
 static inline u32 mc_enable_ce0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 mc_enable_pfifo_enabled_f(void)
 {
@@ -218,7 +220,7 @@ static inline u32 mc_enable_pfb_enabled_f(void)
 }
 static inline u32 mc_enable_ce2_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 mc_enable_ce2_enabled_f(void)
 {
@@ -254,7 +256,7 @@ static inline u32 mc_enable_pb_0_f(u32 v)
 }
 static inline u32 mc_enable_pb_0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 mc_enable_pb_0_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PBDMA_GM20B_H
 #define NVGPU_HW_PBDMA_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pbdma_gp_entry1_r(void)
 {
 	return 0x10000004U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PERF_GM20B_H
 #define NVGPU_HW_PERF_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 perf_pmmsys_base_v(void)
 {
 	return 0x001b0000U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRAM_GM20B_H
 #define NVGPU_HW_PRAM_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pram_data032_r(u32 i)
 {
 	return 0x00700000U + i*4U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h

@@ -56,13 +56,15 @@
 #ifndef NVGPU_HW_PRI_RINGMASTER_GM20B_H
 #define NVGPU_HW_PRI_RINGMASTER_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringmaster_command_r(void)
 {
 	return 0x0012004cU;
 }
 static inline u32 pri_ringmaster_command_cmd_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 pri_ringmaster_command_cmd_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GM20B_H
 #define NVGPU_HW_PRI_RINGSTATION_GPC_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
 	return 0x00128300U + i*4U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GM20B_H
 #define NVGPU_HW_PRI_RINGSTATION_SYS_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {
 	return 0x00122300U + i*4U;
@@ -66,7 +68,7 @@ static inline u32 pri_ringstation_sys_decode_config_r(void)
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PROJ_GM20B_H
 #define NVGPU_HW_PROJ_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 proj_gpc_base_v(void)
 {
 	return 0x00500000U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PWR_GM20B_H
 #define NVGPU_HW_PWR_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pwr_falcon_irqsset_r(void)
 {
 	return 0x0010a000U;
@@ -302,7 +304,7 @@ static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -314,7 +316,7 @@ static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -338,7 +340,7 @@ static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
 {
@@ -390,11 +392,11 @@ static inline u32 pwr_falcon_dmactl_r(void)
 }
 static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_falcon_hwcfg_r(void)
 {
@@ -450,7 +452,7 @@ static inline u32 pwr_falcon_exterrstat_r(void)
 }
 static inline u32 pwr_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
 {
@@ -474,7 +476,7 @@ static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -506,7 +508,7 @@ static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 {
@@ -514,7 +516,7 @@ static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
 {
@@ -578,7 +580,7 @@ static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
 }
 static inline u32 pwr_pmu_mutex_id_release_value_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
 {
@@ -698,7 +700,7 @@ static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
 }
 static inline u32 pwr_pmu_idle_ctrl_value_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
 {
@@ -710,7 +712,7 @@ static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
@@ -810,7 +812,7 @@ static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
 }
 static inline u32 pwr_fbif_transcfg_mem_type_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_RAM_GM20B_H
 #define NVGPU_HW_RAM_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ram_in_ramfc_s(void)
 {
 	return 4096U;
@@ -98,7 +100,7 @@ static inline u32 ram_in_big_page_size_f(u32 v)
 }
 static inline u32 ram_in_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 ram_in_big_page_size_w(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_THERM_GM20B_H
 #define NVGPU_HW_THERM_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 therm_use_a_r(void)
 {
 	return 0x00020798U;
@@ -134,7 +136,7 @@ static inline u32 therm_gate_ctrl_r(u32 i)
 }
 static inline u32 therm_gate_ctrl_eng_clk_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
 {
@@ -150,7 +152,7 @@ static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
 }
 static inline u32 therm_gate_ctrl_blk_clk_m(void)
 {
-	return 0x3U << 2U;
+	return U32(0x3U) << 2U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
 {
@@ -162,7 +164,7 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
 }
 static inline u32 therm_gate_ctrl_eng_pwr_m(void)
 {
-	return 0x3U << 4U;
+	return U32(0x3U) << 4U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
 {
@@ -182,7 +184,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
 {
-	return 0x1fU << 8U;
+	return U32(0x1fU) << 8U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 {
@@ -190,7 +192,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
 {
-	return 0x7U << 13U;
+	return U32(0x7U) << 13U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 {
@@ -198,7 +200,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 {
@@ -206,7 +208,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
 {
-	return 0xfU << 20U;
+	return U32(0xfU) << 20U;
 }
 static inline u32 therm_fecs_idle_filter_r(void)
 {
@@ -214,7 +216,7 @@ static inline u32 therm_fecs_idle_filter_r(void)
 }
 static inline u32 therm_fecs_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_hubmmu_idle_filter_r(void)
 {
@@ -222,7 +224,7 @@ static inline u32 therm_hubmmu_idle_filter_r(void)
 }
 static inline u32 therm_hubmmu_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_clk_slowdown_r(u32 i)
 {
@@ -234,7 +236,7 @@ static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
 }
 static inline u32 therm_clk_slowdown_idle_factor_m(void)
 {
-	return 0x3fU << 16U;
+	return U32(0x3fU) << 16U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
 {
@@ -254,7 +256,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
 {
@@ -278,7 +280,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 {
@@ -286,7 +288,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
 {
-	return 0x3fU << 12U;
+	return U32(0x3fU) << 12U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 {
@@ -294,7 +296,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
 {
-	return 0x3fU << 18U;
+	return U32(0x3fU) << 18U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 {
@@ -302,7 +304,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
 {
-	return 0x3fU << 24U;
+	return U32(0x3fU) << 24U;
 }
 static inline u32 therm_grad_stepping0_r(void)
 {
@@ -318,7 +320,7 @@ static inline u32 therm_grad_stepping0_feature_f(u32 v)
 }
 static inline u32 therm_grad_stepping0_feature_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 therm_grad_stepping0_feature_v(u32 r)
 {
@@ -346,7 +348,7 @@ static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
 }
 static inline u32 therm_clk_timing_grad_slowdown_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TIMER_GM20B_H
 #define NVGPU_HW_TIMER_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 timer_pri_timeout_r(void)
 {
 	return 0x00009080U;
@@ -66,7 +68,7 @@ static inline u32 timer_pri_timeout_period_f(u32 v)
 }
 static inline u32 timer_pri_timeout_period_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 timer_pri_timeout_period_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 timer_pri_timeout_en_f(u32 v)
 }
 static inline u32 timer_pri_timeout_en_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 timer_pri_timeout_en_v(u32 r)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h

@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TOP_GM20B_H
 #define NVGPU_HW_TOP_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 top_num_gpcs_r(void)
 {
 	return 0x00022430U;

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h

@@ -56,13 +56,15 @@
 #ifndef NVGPU_HW_TRIM_GM20B_H
 #define NVGPU_HW_TRIM_GM20B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 trim_sys_gpcpll_cfg_r(void)
 {
 	return 0x00137000U;
 }
 static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
 }
 static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
 {
@@ -90,7 +92,7 @@ static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
 }
 static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
 {
@@ -106,7 +108,7 @@ static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
 }
 static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
 {
@@ -134,7 +136,7 @@ static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
 {
@@ -146,7 +148,7 @@ static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
 {
@@ -158,7 +160,7 @@ static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
 {
-	return 0x3fU << 16U;
+	return U32(0x3fU) << 16U;
 }
 static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
 {
@@ -170,7 +172,7 @@ static inline u32 trim_sys_sel_vco_r(void)
 }
 static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
 {
@@ -202,7 +204,7 @@ static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
 }
 static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
 {
@@ -222,7 +224,7 @@ static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
 }
 static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
 {
-	return 0x3fU << 8U;
+	return U32(0x3fU) << 8U;
 }
 static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
 {
@@ -234,7 +236,7 @@ static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
 }
 static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
 {
@@ -278,7 +280,7 @@ static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
 {
@@ -290,7 +292,7 @@ static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
 {
@@ -302,7 +304,7 @@ static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
 {
-	return 0xffU << 24U;
+	return U32(0xffU) << 24U;
 }
 static inline u32 trim_sys_gpcpll_cfg3_r(void)
 {
@@ -314,7 +316,7 @@ static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
 {
-	return 0x1ffU << 0U;
+	return U32(0x1ffU) << 0U;
 }
 static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
 {
@@ -322,7 +324,7 @@ static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
 {
@@ -338,7 +340,7 @@ static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
 {
-	return 0x7fU << 0U;
+	return U32(0x7fU) << 0U;
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
 {
@@ -350,7 +352,7 @@ static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
 {
-	return 0x7fU << 8U;
+	return U32(0x7fU) << 8U;
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
 {
@@ -362,7 +364,7 @@ static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
 {
-	return 0x3fU << 16U;
+	return U32(0x3fU) << 16U;
 }
 static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
 {
@@ -370,7 +372,7 @@ static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
 }
 static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
 {
@@ -386,7 +388,7 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
 {
-	return 0x7fU << 0U;
+	return U32(0x7fU) << 0U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
 {
@@ -394,7 +396,7 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
 {
@@ -402,7 +404,7 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
 {
-	return 0x7fU << 8U;
+	return U32(0x7fU) << 8U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
 {
@@ -410,7 +412,7 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
 {
@@ -418,7 +420,7 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
 {
-	return 0xfffU << 16U;
+	return U32(0xfffU) << 16U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
 {
@@ -426,15 +428,15 @@ static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
 }
 static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
 {
@@ -450,7 +452,7 @@ static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
 }
 static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
 {
-	return 0x1U << 22U;
+	return U32(0x1U) << 22U;
 }
 static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
 {
@@ -462,7 +464,7 @@ static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
 }
 static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
 {
@@ -490,7 +492,7 @@ static inline u32 trim_sys_bypassctrl_r(void)
 }
 static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
 {