gpu: nvgpu: API to access fb memory

Add IOCTL API NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
to read/write fb/vidmem memory

Interface will accept dmabuf_fd of the buffer in vidmem,
offset into the buffer to access, temporary buffer
to copy data across API, size of read/write and
command indicating either read or write operation

API will first parse all the inputs, and then call
gk20a_vidbuf_access_memory() to complete fb access

gk20a_vidbuf_access_memory() will then just use
gk20a_mem_rd_n() or gk20a_mem_wr_n() depending
on the command issued

Bug 1804714
Jira DNVGPU-192

Change-Id: Iba3c42410abe12c2884d3b603fa33d27782e4c56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1255556
(cherry picked from commit 2c49a8a79d93fc526adbf6f808484fa9a3fa2498)
Reviewed-on: http://git-master/r/1260471
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c

@@ -21,6 +21,7 @@
 #include <linux/cdev.h>
 #include <linux/uaccess.h>
 #include <linux/nvhost.h>
+#include <linux/dma-buf.h>
 #include <uapi/linux/nvgpu.h>
 
 #include "gk20a.h"
@@ -789,6 +790,84 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s,
 	return err;
 }
 
+static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s,
+		struct nvgpu_dbg_gpu_access_fb_memory_args *args)
+{
+	struct gk20a *g = dbg_s->g;
+	struct dma_buf *dmabuf;
+	void __user *user_buffer = (void __user *)(uintptr_t)args->buffer;
+	void *buffer;
+	u64 size, access_size, offset;
+	u64 access_limit_size = SZ_4K;
+	int err = 0;
+
+	if ((args->offset & 3) || (!args->size) || (args->size & 3))
+		return -EINVAL;
+
+	dmabuf = dma_buf_get(args->dmabuf_fd);
+	if (IS_ERR(dmabuf))
+		return -EINVAL;
+
+	if ((args->offset > dmabuf->size) ||
+	    (args->size > dmabuf->size) ||
+	    (args->offset + args->size > dmabuf->size)) {
+		err = -EINVAL;
+		goto fail_dmabuf_put;
+	}
+
+	buffer = nvgpu_alloc(access_limit_size, true);
+	if (!buffer) {
+		err = -ENOMEM;
+		goto fail_dmabuf_put;
+	}
+
+	size = args->size;
+	offset = 0;
+
+	err = gk20a_busy(g->dev);
+	if (err)
+		goto fail_free_buffer;
+
+	while (size) {
+		/* Max access size of access_limit_size in one loop */
+		access_size = min(access_limit_size, size);
+
+		if (args->cmd ==
+		    NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_WRITE) {
+			err = copy_from_user(buffer, user_buffer + offset,
+					     access_size);
+			if (err)
+				goto fail_idle;
+		}
+
+		err = gk20a_vidbuf_access_memory(g, dmabuf, buffer,
+					 args->offset + offset, access_size,
+					 args->cmd);
+		if (err)
+			goto fail_idle;
+
+		if (args->cmd ==
+		    NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ) {
+			err = copy_to_user(user_buffer + offset,
+					   buffer, access_size);
+			if (err)
+				goto fail_idle;
+		}
+
+		size -= access_size;
+		offset += access_size;
+	}
+
+fail_idle:
+	gk20a_idle(g->dev);
+fail_free_buffer:
+	nvgpu_free(buffer);
+fail_dmabuf_put:
+	dma_buf_put(dmabuf);
+
+	return err;
+}
+
 long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
 			     unsigned long arg)
 {
@@ -911,6 +990,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
 		      (struct nvgpu_dbg_gpu_suspend_resume_contexts_args *)buf);
 		break;
 
+	case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY:
+		err = nvgpu_dbg_gpu_ioctl_access_fb_memory(dbg_s,
+			(struct nvgpu_dbg_gpu_access_fb_memory_args *)buf);
+		break;
+
 	default:
 		gk20a_err(dev_from_gk20a(g),
 			   "unrecognized dbg gpu ioctl cmd: 0x%x",

drivers/gpu/nvgpu/gk20a/mm_gk20a.c

@@ -2301,6 +2301,39 @@ int gk20a_vidmem_get_space(struct gk20a *g, u64 *space)
 #endif
 }
 
+int gk20a_vidbuf_access_memory(struct gk20a *g, struct dma_buf *dmabuf,
+		void *buffer, u64 offset, u64 size, u32 cmd)
+{
+#if defined(CONFIG_GK20A_VIDMEM)
+	struct gk20a_vidmem_buf *vidmem_buf;
+	struct mem_desc *mem;
+	int err = 0;
+
+	if (gk20a_dmabuf_aperture(g, dmabuf) != APERTURE_VIDMEM)
+		return -EINVAL;
+
+	vidmem_buf = dmabuf->priv;
+	mem = vidmem_buf->mem;
+
+	switch (cmd) {
+	case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ:
+		gk20a_mem_rd_n(g, mem, offset, buffer, size);
+		break;
+
+	case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_WRITE:
+		gk20a_mem_wr_n(g, mem, offset, buffer, size);
+		break;
+
+	default:
+		err = -EINVAL;
+	}
+
+	return err;
+#else
+	return -ENOSYS;
+#endif
+}
+
 static u64 gk20a_mm_get_align(struct gk20a *g, struct scatterlist *sgl,
 			      enum gk20a_aperture aperture)
 {

drivers/gpu/nvgpu/gk20a/mm_gk20a.h

@@ -762,6 +762,8 @@ void gk20a_vm_mapping_batch_finish_locked(
 
 int gk20a_vidmem_buf_alloc(struct gk20a *g, size_t bytes);
 int gk20a_vidmem_get_space(struct gk20a *g, u64 *space);
+int gk20a_vidbuf_access_memory(struct gk20a *g, struct dma_buf *dmabuf,
+		void *buffer, u64 offset, u64 size, u32 cmd);
 
 /* Note: batch may be NULL if map op is not part of a batch */
 int gk20a_vm_map_buffer(struct vm_gk20a *vm,

include/uapi/linux/nvgpu.h

@@ -917,11 +917,28 @@ struct nvgpu_dbg_gpu_suspend_resume_contexts_args {
 	_IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 18, struct nvgpu_dbg_gpu_suspend_resume_contexts_args)
 
 
+#define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ	1
+#define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_WRITE	2
+
+struct nvgpu_dbg_gpu_access_fb_memory_args {
+	__u32 cmd;       /* in: either read or write */
+
+	__s32 dmabuf_fd; /* in: dmabuf fd of the buffer in FB */
+	__u64 offset;    /* in: offset within buffer in FB, should be 4B aligned */
+
+	__u64 buffer;    /* in/out: temp buffer to read/write from */
+	__u64 size;      /* in: size of the buffer i.e. size of read/write in bytes, should be 4B aligned */
+};
+
+#define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY	\
+	_IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 19, struct nvgpu_dbg_gpu_access_fb_memory_args)
+
+
 #define NVGPU_DBG_GPU_IOCTL_LAST		\
-	_IOC_NR(NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS)
+	_IOC_NR(NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY)
 
 #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE		\
-	sizeof(struct nvgpu_dbg_gpu_perfbuf_map_args)
+	sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args)
 
 /*
  * /dev/nvhost-gpu device