diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
index b0a098208..dd01b3376 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
@@ -73,4 +73,6 @@ u32 ga10b_pbdma_intr_0_en_set_tree_mask(void);
 u32 ga10b_pbdma_intr_0_en_clear_tree_mask(void);
 u32 ga10b_pbdma_intr_1_en_set_tree_mask(void);
 u32 ga10b_pbdma_intr_1_en_clear_tree_mask(void);
+void ga10b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
+		u32 pbdma_intr_0);
 #endif /* NVGPU_PBDMA_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
index e2f52dbbf..a1264273b 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
@@ -293,7 +293,7 @@ u32 ga10b_pbdma_read_data(struct gk20a *g, u32 pbdma_id)
 	return nvgpu_readl(g, pbdma_hdr_shadow_r(pbdma_id));
 }
 
-static void report_pbdma_error(struct gk20a *g, u32 pbdma_id,
+void ga10b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
 		u32 pbdma_intr_0)
 {
 	u32 err_type = GPU_HOST_INVALID_ERROR;
@@ -501,7 +501,11 @@ bool ga10b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
 				 pbdma_id);
 		recover = true;
 	}
-	report_pbdma_error(g, pbdma_id, pbdma_intr_0);
+
+	if (g->ops.pbdma.report_error != NULL) {
+		g->ops.pbdma.report_error(g, pbdma_id, pbdma_intr_0);
+	}
+
 	return recover;
 }
 
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h
index 8b3a98362..d364bfa4b 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,5 +39,7 @@ u32 gv11b_pbdma_get_fc_pb_header(void);
 u32 gv11b_pbdma_get_fc_target(const struct nvgpu_device *dev);
 u32 gv11b_pbdma_set_channel_info_veid(u32 subctx_id);
 u32 gv11b_pbdma_config_userd_writeback_enable(u32 v);
+void gv11b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
+		u32 pbdma_intr_0);
 
 #endif /* NVGPU_PBDMA_GV11B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c
index 43408db27..f39493737 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,7 +33,7 @@
 #include "pbdma_gm20b.h"
 #include "pbdma_gv11b.h"
 
-static void report_pbdma_error(struct gk20a *g, u32 pbdma_id,
+void gv11b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
 		u32 pbdma_intr_0)
 {
 	u32 err_type = GPU_HOST_INVALID_ERROR;
@@ -149,7 +149,11 @@ bool gv11b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
 				 pbdma_id);
 		recover = true;
 	}
-	report_pbdma_error(g, pbdma_id, pbdma_intr_0);
+
+	if (g->ops.pbdma.report_error != NULL) {
+		g->ops.pbdma.report_error(g, pbdma_id, pbdma_intr_0);
+	}
+
 	return recover;
 }
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 121418cc9..f4aba93bd 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -1078,6 +1078,7 @@ static const struct gops_pbdma ga100_ops_pbdma = {
 	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
 	.set_channel_info_chid = ga10b_pbdma_set_channel_info_chid,
 	.set_intr_notify = ga10b_pbdma_set_intr_notify,
+	.report_error = ga10b_pbdma_report_error,
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.pbdma_force_ce_split = ga100_pbdma_force_ce_split,
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index 689230f40..f91e45240 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1096,6 +1096,7 @@ static const struct gops_pbdma ga10b_ops_pbdma = {
 	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
 	.set_channel_info_chid = ga10b_pbdma_set_channel_info_chid,
 	.set_intr_notify = ga10b_pbdma_set_intr_notify,
+	.report_error = ga10b_pbdma_report_error,
 	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
 	.get_mmu_fault_id = ga10b_pbdma_get_mmu_fault_id,
 	.get_num_of_pbdmas = ga10b_pbdma_get_num_of_pbdmas,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 4e0f9ceeb..57d5996d9 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B Tegra HAL interface
  *
- * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -919,6 +919,7 @@ static const struct gops_pbdma gv11b_ops_pbdma = {
 	.get_config_auth_level_privileged = gp10b_pbdma_get_config_auth_level_privileged,
 	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
 	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
+	.report_error = gv11b_pbdma_report_error,
 };
 
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index d52ad5fdd..a2f3e487d 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1,7 +1,7 @@
 /*
  * TU104 Tegra HAL interface
  *
- * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -976,6 +976,7 @@ static const struct gops_pbdma tu104_ops_pbdma = {
 	.get_config_auth_level_privileged = gp10b_pbdma_get_config_auth_level_privileged,
 	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
 	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
+	.report_error = gv11b_pbdma_report_error,
 };
 
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
index eddda70d3..eaf49320f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
@@ -90,6 +90,8 @@ struct gops_pbdma {
 	u32 (*set_intr_notify)(u32 eng_intr_vector);
 	u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
 	u32 (*get_num_of_pbdmas)(void);
+	void (*report_error)(struct gk20a *g, u32 pbdma_id,
+		u32 pbdma_intr_0);
 
 	/** NON FUSA */
 	void (*syncpt_debug_dump)(struct gk20a *g,