gpu: nvgpu: add missing busy calls for ctrl ioctls

The following ioctls:

- NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
- NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE
- NVGPU_GPU_IOCTL_TRIGGER_SUSPEND
- NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS

access hardware registers, so they should make sure that the gpu is
powered on first. Add gk20a_{busy,idle}() pairs for them.

Bug 1849661

Change-Id: I7deabf4a2c1c7d069a6134233f8e86df0a2722c8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1461449
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2017-04-12 15:29:37 +03:00
committed by mobile promotions
parent f4e3628343
commit afe12a49f7

View File

@@ -393,16 +393,23 @@ static int nvgpu_gpu_ioctl_trigger_suspend(struct gk20a *g)
{ {
int err; int err;
err = gk20a_busy(g);
if (err)
return err;
nvgpu_mutex_acquire(&g->dbg_sessions_lock); nvgpu_mutex_acquire(&g->dbg_sessions_lock);
err = g->ops.gr.trigger_suspend(g); err = g->ops.gr.trigger_suspend(g);
nvgpu_mutex_release(&g->dbg_sessions_lock); nvgpu_mutex_release(&g->dbg_sessions_lock);
gk20a_idle(g);
return err; return err;
} }
static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
struct nvgpu_gpu_wait_pause_args *args) struct nvgpu_gpu_wait_pause_args *args)
{ {
int err = 0; int err;
struct warpstate *w_state; struct warpstate *w_state;
u32 sm_count, size; u32 sm_count, size;
@@ -412,6 +419,10 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
if (!w_state) if (!w_state)
return -ENOMEM; return -ENOMEM;
err = gk20a_busy(g);
if (err)
goto out_free;
nvgpu_mutex_acquire(&g->dbg_sessions_lock); nvgpu_mutex_acquire(&g->dbg_sessions_lock);
g->ops.gr.wait_for_pause(g, w_state); g->ops.gr.wait_for_pause(g, w_state);
@@ -422,23 +433,45 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
} }
nvgpu_mutex_release(&g->dbg_sessions_lock); nvgpu_mutex_release(&g->dbg_sessions_lock);
gk20a_idle(g);
out_free:
nvgpu_kfree(g, w_state); nvgpu_kfree(g, w_state);
return err; return err;
} }
static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g) static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g)
{ {
int err = 0; int err;
err = gk20a_busy(g);
if (err)
return err;
nvgpu_mutex_acquire(&g->dbg_sessions_lock); nvgpu_mutex_acquire(&g->dbg_sessions_lock);
err = g->ops.gr.resume_from_pause(g); err = g->ops.gr.resume_from_pause(g);
nvgpu_mutex_release(&g->dbg_sessions_lock); nvgpu_mutex_release(&g->dbg_sessions_lock);
gk20a_idle(g);
return err; return err;
} }
static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g) static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g)
{ {
return g->ops.gr.clear_sm_errors(g); int err;
err = gk20a_busy(g);
if (err)
return err;
err = g->ops.gr.clear_sm_errors(g);
gk20a_idle(g);
return err;
} }
static int nvgpu_gpu_ioctl_has_any_exception( static int nvgpu_gpu_ioctl_has_any_exception(