diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c98fec48a..03510a16b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1133,7 +1133,8 @@ struct gpu_ops {
 	struct {
 		int (*exec_regops)(struct dbg_session_gk20a *dbg_s,
 			    struct nvgpu_dbg_reg_op *ops,
-			    u64 num_ops);
+			    u64 num_ops,
+			    bool *is_current_ctx);
 		const struct regop_offset_range* (
 				*get_global_whitelist_ranges)(void);
 		u64 (*get_global_whitelist_ranges_count)(void);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a40d93fd2..f3b580e46 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 			  struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
-			  u32 num_ctx_wr_ops, u32 num_ctx_rd_ops)
+			  u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
+			  bool *is_curr_ctx)
 {
 	struct gk20a *g = ch->g;
 	int err, tmp_err;
@@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 	}
 
 	ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch);
-
+	if (is_curr_ctx != NULL) {
+		*is_curr_ctx = ch_is_curr_ctx;
+	}
 	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d",
 		  ch_is_curr_ctx);
 
@@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
 		i++;
 	}
 
-	err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0);
+	err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
 	if (err) {
 		nvgpu_err(g, "Failed to access register");
 	}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 4f83bba34..617aad34e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -616,7 +616,8 @@ int gk20a_gr_suspend(struct gk20a *g);
 struct nvgpu_dbg_reg_op;
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 			  struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
-			  u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
+			  u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
+			  bool *is_curr_ctx);
 int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 			    struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
 			    u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index 80d27c258..0aec4f868 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -89,7 +89,8 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 		      struct nvgpu_dbg_reg_op *ops,
-		      u64 num_ops)
+		      u64 num_ops,
+		      bool *is_current_ctx)
 {
 	int err = 0;
 	unsigned int i;
@@ -219,7 +220,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 
 	if (ctx_wr_count | ctx_rd_count) {
 		err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops,
-					    ctx_wr_count, ctx_rd_count);
+					    ctx_wr_count, ctx_rd_count,
+					    is_current_ctx);
 		if (err) {
 			nvgpu_warn(g, "failed to perform ctx ops\n");
 			goto clean_up;
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
index 0fb108a4f..967058798 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -77,7 +77,8 @@ struct regop_offset_range {
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 		      struct nvgpu_dbg_reg_op *ops,
-		      u64 num_ops);
+		      u64 num_ops,
+		      bool *is_current_ctx);
 
 /* turn seriously unwieldy names -> something shorter */
 #define REGOP(x) NVGPU_DBG_REG_OP_##x
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 0938e2ed9..450775b10 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3377,7 +3377,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
 		i++;
 	}
 
-	err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0);
+	err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
 	if (err) {
 		nvgpu_err(g, "Failed to access register\n");
 	}
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 9ea681b1a..1eace94b9 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -869,6 +869,9 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
 	struct gk20a *g = dbg_s->g;
 	struct channel_gk20a *ch;
 
+	bool is_current_ctx;
+
+
 	nvgpu_log_fn(g, "%d ops, max fragment %d", args->num_ops, g->dbg_regops_tmp_buf_ops);
 
 	if (args->num_ops > NVGPU_IOCTL_DBG_REG_OPS_LIMIT) {
@@ -954,11 +957,15 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
 				break;
 
 			err = g->ops.regops.exec_regops(
-				dbg_s, g->dbg_regops_tmp_buf, num_ops);
+				dbg_s, g->dbg_regops_tmp_buf, num_ops, &is_current_ctx);
 
 			if (err) {
 				break;
-                        }
+			}
+
+			if (ops_offset == 0) {
+				args->gr_ctx_resident = is_current_ctx;
+			}
 
 			err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf,
 					linux_fragment, num_ops);
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
index d188f5406..ca8d2872f 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
@@ -33,7 +33,8 @@
 
 int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
 		      struct nvgpu_dbg_reg_op *ops,
-		      u64 num_ops)
+		      u64 num_ops,
+		      bool *is_current_ctx)
 {
 	struct channel_gk20a *ch;
 	struct tegra_vgpu_cmd_msg msg;
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
index 90645e596..7a1050ce6 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
@@ -30,7 +30,8 @@ struct gk20a;
 
 int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
 		      struct nvgpu_dbg_reg_op *ops,
-		      u64 num_ops);
+		      u64 num_ops,
+		      bool *is_current_ctx);
 int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
 bool vgpu_check_and_set_global_reservation(
 				struct dbg_session_gk20a *dbg_s,
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index b1dc4df4a..1a275b351 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -1169,7 +1169,7 @@ struct nvgpu_dbg_gpu_reg_op {
 struct nvgpu_dbg_gpu_exec_reg_ops_args {
 	__u64 ops; /* pointer to nvgpu_reg_op operations */
 	__u32 num_ops;
-	__u32 _pad0[1];
+	__u32 gr_ctx_resident;
 };
 
 #define NVGPU_DBG_GPU_IOCTL_REG_OPS					\