diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c
index d6dbe1952..2534f52b6 100644
--- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c
+++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c
@@ -58,7 +58,7 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 {
 	u32 clkwhich;
 	struct nvgpu_pmu_perf_pstate_clk_info *p0_info;
-	struct nvgpu_avfsfllobjs *pfllobjs =  g->pmu->clk_pmu->avfs_fllobjs;
+	u16 max_min_freq_mhz;
 	u16 limit_min_mhz;
 	u16 gpcclk_cap_mhz;
 	bool error_status = false;
@@ -90,11 +90,13 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 	limit_min_mhz = p0_info->min_mhz;
 	gpcclk_cap_mhz = p0_info->max_mhz;
 
+	max_min_freq_mhz = nvgpu_pmu_clk_fll_get_min_max_freq(g);
 	/* WAR for DVCO min */
 	if (api_domain == CTRL_CLK_DOMAIN_GPCCLK) {
-		if ((pfllobjs->max_min_freq_mhz != 0U) &&
-			(pfllobjs->max_min_freq_mhz >= limit_min_mhz)) {
-			limit_min_mhz = pfllobjs->max_min_freq_mhz + 1U;
+		if ((max_min_freq_mhz != 0U) &&
+			(max_min_freq_mhz >= limit_min_mhz)) {
+			limit_min_mhz = nvgpu_safe_cast_u32_to_u16(
+				nvgpu_safe_add_u32(max_min_freq_mhz, 1U));
 		}
 		if ((g->clk_arb->gpc_cap_clkmhz != 0U) &&
 			(p0_info->max_mhz > g->clk_arb->gpc_cap_clkmhz )) {
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
index d18a2cccd..3ac00ddb6 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
@@ -36,7 +36,7 @@
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK	0x1FU
 
 static int devinit_get_fll_device_table(struct gk20a *g,
-		struct nvgpu_avfsfllobjs *pfllobjs);
+		struct clk_avfs_fll_objs *pfllobjs);
 static struct fll_device *construct_fll_device(struct gk20a *g,
 		void *pargs);
 static int fll_device_init_pmudata_super(struct gk20a *g,
@@ -50,12 +50,12 @@ static u8 clk_get_fll_lut_vf_num_entries(struct nvgpu_clk_pmupstate *pclk)
 	return ((pclk)->avfs_fllobjs->lut_num_entries);
 }
 
-static u32 clk_get_fll_lut_min_volt(struct nvgpu_clk_pmupstate *pclk)
+u32 nvgpu_pmu_clk_fll_get_lut_min_volt(struct nvgpu_clk_pmupstate *pclk)
 {
 	return ((pclk)->avfs_fllobjs->lut_min_voltage_uv);
 }
 
-static u32 clk_get_fll_lut_step_size(struct nvgpu_clk_pmupstate *pclk)
+u32 nvgpu_pmu_clk_fll_get_lut_step_size(struct nvgpu_clk_pmupstate *pclk)
 {
 	return ((pclk)->avfs_fllobjs->lut_step_size_uv);
 }
@@ -67,7 +67,7 @@ static int _clk_fll_devgrp_pmudatainit_super(struct gk20a *g,
 	struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct nvgpu_avfsfllobjs *pfll_objs = (struct nvgpu_avfsfllobjs *)
+	struct clk_avfs_fll_objs *pfll_objs = (struct clk_avfs_fll_objs *)
 		pboardobjgrp;
 	int status = 0;
 
@@ -138,7 +138,7 @@ int clk_fll_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
-	struct nvgpu_avfsfllobjs *pfllobjs;
+	struct clk_avfs_fll_objs *pfllobjs;
 	struct fll_device *pfll;
 	struct fll_device *pfll_master;
 	struct fll_device *pfll_local;
@@ -171,7 +171,7 @@ int clk_fll_sw_setup(struct gk20a *g)
 	pboardobjgrp->pmudatainit  = _clk_fll_devgrp_pmudatainit_super;
 	pboardobjgrp->pmudatainstget  = _clk_fll_devgrp_pmudata_instget;
 	pboardobjgrp->pmustatusinstget  = _clk_fll_devgrp_pmustatus_instget;
-	pfllobjs = (struct nvgpu_avfsfllobjs *)pboardobjgrp;
+	pfllobjs = (struct clk_avfs_fll_objs *)pboardobjgrp;
 	pfllobjs->lut_num_entries = g->ops.clk.lut_num_entries;
 	pfllobjs->lut_step_size_uv = CTRL_CLK_VIN_STEP_SIZE_UV;
 	pfllobjs->lut_min_voltage_uv = CTRL_CLK_LUT_MIN_VOLTAGE_UV;
@@ -255,7 +255,7 @@ int clk_fll_pmu_setup(struct gk20a *g)
 }
 
 static int devinit_get_fll_device_table(struct gk20a *g,
-		struct nvgpu_avfsfllobjs *pfllobjs)
+		struct clk_avfs_fll_objs *pfllobjs)
 {
 	int status = 0;
 	u8 *fll_table_ptr = NULL;
@@ -425,7 +425,7 @@ static u32 clk_get_vbios_clk_domain(u32 vbios_domain)
 }
 
 static int lutbroadcastslaveregister(struct gk20a *g,
-		struct nvgpu_avfsfllobjs *pfllobjs, struct fll_device *pfll,
+		struct clk_avfs_fll_objs *pfllobjs, struct fll_device *pfll,
 		struct fll_device *pfll_slave)
 {
 	if (pfll->clk_domain != pfll_slave->clk_domain) {
@@ -596,7 +596,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
 
 u8 nvgpu_pmu_clk_fll_get_fmargin_idx(struct gk20a *g)
 {
-	struct nvgpu_avfsfllobjs *pfllobjs =  g->pmu->clk_pmu->avfs_fllobjs;
+	struct clk_avfs_fll_objs *pfllobjs =  g->pmu->clk_pmu->avfs_fllobjs;
 	u8 fmargin_idx;
 
 	fmargin_idx = pfllobjs->freq_margin_vfe_idx;
@@ -606,6 +606,15 @@ u8 nvgpu_pmu_clk_fll_get_fmargin_idx(struct gk20a *g)
 	return fmargin_idx;
 }
 
+u16 nvgpu_pmu_clk_fll_get_min_max_freq(struct gk20a *g)
+{
+	if ((g->pmu->clk_pmu != NULL) &&
+			(g->pmu->clk_pmu->avfs_fllobjs != NULL)) {
+		return (g->pmu->clk_pmu->avfs_fllobjs->max_min_freq_mhz);
+	}
+	return 0;
+}
+
 int clk_fll_init_pmupstate(struct gk20a *g)
 {
 	/* If already allocated, do not re-allocate */
@@ -625,9 +634,9 @@ int clk_fll_init_pmupstate(struct gk20a *g)
 	g->pmu->clk_pmu->get_fll_lut_vf_num_entries =
 			clk_get_fll_lut_vf_num_entries;
 	g->pmu->clk_pmu->get_fll_lut_min_volt =
-			clk_get_fll_lut_min_volt;
+			nvgpu_pmu_clk_fll_get_lut_min_volt;
 	g->pmu->clk_pmu->get_fll_lut_step_size =
-			clk_get_fll_lut_step_size;
+			nvgpu_pmu_clk_fll_get_lut_step_size;
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
index 8c0d76389..8da7e5976 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
@@ -27,8 +27,18 @@
 struct gk20a;
 struct fll_device;
 
+struct clk_avfs_fll_objs {
+	struct boardobjgrp_e32 super;
+	struct boardobjgrpmask_e32 lut_prog_master_mask;
+	u32 lut_step_size_uv;
+	u32 lut_min_voltage_uv;
+	u8 lut_num_entries;
+	u16 max_min_freq_mhz;
+	u8 freq_margin_vfe_idx;
+};
+
 typedef int fll_lut_broadcast_slave_register(struct gk20a *g,
-	struct nvgpu_avfsfllobjs *pfllobjs,
+	struct clk_avfs_fll_objs *pfllobjs,
 	struct fll_device *pfll,
 	struct fll_device *pfll_slave);
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
index f3666b816..7bb6d3864 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
@@ -127,7 +127,7 @@
 #define FREQ_STEP_SIZE_MHZ      15U
 
 struct gk20a;
-struct nvgpu_avfsfllobjs;
+struct clk_avfs_fll_objs;
 struct nvgpu_clk_domains;
 struct nvgpu_clk_progs;
 struct nvgpu_clk_vf_points;
@@ -238,19 +238,9 @@ struct nvgpu_set_fll_clk {
 	u8 target_regime_id_host;
 };
 
-struct nvgpu_avfsfllobjs {
-	struct boardobjgrp_e32 super;
-	struct boardobjgrpmask_e32 lut_prog_master_mask;
-	u32 lut_step_size_uv;
-	u32 lut_min_voltage_uv;
-	u8 lut_num_entries;
-	u16 max_min_freq_mhz;
-	u8 freq_margin_vfe_idx;
-};
-
 struct nvgpu_clk_pmupstate {
 	struct nvgpu_avfsvinobjs *avfs_vinobjs;
-	struct nvgpu_avfsfllobjs *avfs_fllobjs;
+	struct clk_avfs_fll_objs *avfs_fllobjs;
 	struct nvgpu_clk_domains *clk_domainobjs;
 	struct nvgpu_clk_progs *clk_progobjs;
 	struct nvgpu_clk_vf_points *clk_vf_pointobjs;
@@ -367,4 +357,7 @@ int nvgpu_clk_arb_find_slave_points(struct nvgpu_clk_arb *arb,
 int nvgpu_clk_vf_point_cache(struct gk20a *g);
 int nvgpu_clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx,
 	u32 *pclkmhz, u32 *pvoltuv, u8 railidx);
+u16 nvgpu_pmu_clk_fll_get_min_max_freq(struct gk20a *g);
+u32 nvgpu_pmu_clk_fll_get_lut_step_size(struct nvgpu_clk_pmupstate *pclk);
+u32 nvgpu_pmu_clk_fll_get_lut_min_volt(struct nvgpu_clk_pmupstate *pclk);
 #endif /* NVGPU_PMU_CLK_H */
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
index eb9e04c70..caa667864 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
@@ -53,8 +53,8 @@ static int vftable_show(struct seq_file *s, void *unused)
 	u32 voltage_min_uv, voltage_step_size_uv;
 	u32 gpcclk_clkmhz = 0, gpcclk_voltuv = 0;
 
-	voltage_min_uv = g->pmu->clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
-	voltage_step_size_uv = g->pmu->clk_pmu->avfs_fllobjs->lut_step_size_uv;
+	voltage_min_uv = nvgpu_pmu_clk_fll_get_lut_step_size(g->pmu->clk_pmu);
+	voltage_step_size_uv = nvgpu_pmu_clk_fll_get_lut_step_size(g->pmu->clk_pmu);
 
 	for (index = 0; index < CTRL_CLK_LUT_NUM_ENTRIES_GV10x; index++) {
 		gpcclk_voltuv = voltage_min_uv + index * voltage_step_size_uv;