From b1175cba6407845703c7084d76a31fb410e8e9ce Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 6 Aug 2019 14:57:54 +0530 Subject: [PATCH] gpu: nvgpu: Fix MISRA violations in PMU unit Fix MISRA 8.6 violations in the PMU unit in following files: hal/pmu/pmu_gv11b.h JIRA NVGPU-3885 Change-Id: Ie97e6e78591e72a75ee5bad411ef76943b622917 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/2169140 Reviewed-by: Sagar Kamble Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Philip Elcan Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h index 2291a3f51..89eb46c73 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h @@ -58,8 +58,12 @@ void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g); int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, u32 *etype); bool gv11b_pmu_validate_mem_integrity(struct gk20a *g); + +#ifdef CONFIG_NVGPU_INJECT_HWERR struct nvgpu_hw_err_inject_info_desc * gv11b_pmu_intr_get_err_desc(struct gk20a *g); int gv11b_pmu_inject_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info); +#endif /* CONFIG_NVGPU_INJECT_HWERR */ + #endif /* PMU_GV11B_H */