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gpu: nvgpu: separate tegra fuse read from under CONFIG_NVGPU_TEGRA_FUSE

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tegra_fuse_readl is supported in upstream. Separate out the functions
using this API from the config CONFIG_NVGPU_TEGRA_FUSE.

Following four fuses are defined in downstream kernel repositories in
tegra fuse header. It can be incorporated in upstream if nvgpu starts
reading those fuses using nvmem APIs. Hence define those fuse offsets
in nvgpu itself for now.

1. FUSE_RESERVED_CALIB0_0
2. FUSE_GCPLEX_CONFIG_FUSE_0
3. FUSE_PDI0
4. FUSE_PDI1

Bug 200625647

Change-Id: I8da8c0c3a0682fdab806fa57035fedd29ef22c26
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2369955
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2020-07-02 18:01:31 +05:30
committed by Alex Waterman
parent 04a179a161
commit b117f40f6c
7 changed files with 152 additions and 135 deletions
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66
drivers/gpu/nvgpu/os/linux/fuse.c
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@@ -11,10 +11,12 @@
* more details.
*/
#include <soc/tegra/fuse.h>
#include <nvgpu/fuse.h>
#include <nvgpu/linux/soc_fuse.h>
#include <soc/tegra/fuse.h>
int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
{
*id = tegra_sku_info.gpu_speedo_id;
@@ -22,6 +24,37 @@ int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
return 0;
}
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
}
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
}
int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
{
u32 lo = 0U;
u32 hi = 0U;
int err;
err = tegra_fuse_readl(FUSE_PDI0, &lo);
if (err)
return err;
err = tegra_fuse_readl(FUSE_PDI1, &hi);
if (err)
return err;
*pdi = ((u64)lo) | (((u64)hi) << 32);
return 0;
}
#ifdef CONFIG_NVGPU_TEGRA_FUSE
/*
* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
@@ -46,31 +79,4 @@ void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
}
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
}
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
}
int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
{
u32 lo = 0U;
u32 hi = 0U;
int err;
err = tegra_fuse_readl(FUSE_PDI0, &lo);
if (err)
return err;
err = tegra_fuse_readl(FUSE_PDI1, &hi);
if (err)
return err;
*pdi = ((u64)lo) | (((u64)hi) << 32);
return 0;
}
#endif /* CONFIG_NVGPU_TEGRA_FUSE */