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gpu: nvgpu: refactored struct sim_gk20a

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moved sim buffer(send, recv and msg) from
os-specific structure to OS agnostic structure.

JIRA VQRM-2368

Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702178
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2018-04-25 13:42:16 +05:30
committed by mobile promotions
parent 2a23cd2494
commit b144935644
4 changed files with 26 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/gpu/nvgpu/common/linux/sim.c
View File

@@ -75,12 +75,9 @@ static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
static void gk20a_free_sim_support(struct gk20a *g) static void gk20a_free_sim_support(struct gk20a *g)
{ {
struct sim_gk20a_linux *sim_linux = gk20a_free_sim_buffer(g, &g->sim->send_bfr);
container_of(g->sim, struct sim_gk20a_linux, sim); gk20a_free_sim_buffer(g, &g->sim->recv_bfr);
gk20a_free_sim_buffer(g, &g->sim->msg_bfr);
gk20a_free_sim_buffer(g, &sim_linux->send_bfr);
gk20a_free_sim_buffer(g, &sim_linux->recv_bfr);
gk20a_free_sim_buffer(g, &sim_linux->msg_bfr);
} }
static void gk20a_remove_sim_support(struct sim_gk20a *s) static void gk20a_remove_sim_support(struct sim_gk20a *s)
@@ -91,12 +88,12 @@ static void gk20a_remove_sim_support(struct sim_gk20a *s)
if (sim_linux->regs) if (sim_linux->regs)
sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); sim_writel(s, sim_config_r(), sim_config_mode_disabled_v());
gk20a_free_sim_support(g);
if (sim_linux->regs) { if (sim_linux->regs) {
iounmap(sim_linux->regs); iounmap(sim_linux->regs);
sim_linux->regs = NULL; sim_linux->regs = NULL;
} }
gk20a_free_sim_support(g);
nvgpu_kfree(g, sim_linux); nvgpu_kfree(g, sim_linux);
g->sim = NULL; g->sim = NULL;
@@ -109,8 +106,6 @@ static inline u32 sim_msg_header_size(void)
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va;
@@ -146,8 +141,6 @@ static inline u32 sim_escape_read_hdr_size(void)
static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; cpu_va = (u8 *)sim_linux->send_bfr.cpu_va;
@@ -161,8 +154,6 @@ static int rpc_send_message(struct gk20a *g)
u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
*sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
sim_dma_target_phys_pci_coherent_f() | sim_dma_target_phys_pci_coherent_f() |
@@ -171,7 +162,7 @@ static int rpc_send_message(struct gk20a *g)
sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT);
*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
u64_hi32(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)); u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
@@ -185,8 +176,6 @@ static int rpc_send_message(struct gk20a *g)
static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va;
@@ -197,8 +186,6 @@ static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
static int rpc_recv_poll(struct gk20a *g) static int rpc_recv_poll(struct gk20a *g)
{ {
u64 recv_phys_addr; u64 recv_phys_addr;
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
/* XXX This read is not required (?) */ /* XXX This read is not required (?) */
/*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/
@@ -223,7 +210,7 @@ static int rpc_recv_poll(struct gk20a *g)
(u64)recv_phys_addr_lo << PAGE_SHIFT; (u64)recv_phys_addr_lo << PAGE_SHIFT;
if (recv_phys_addr != if (recv_phys_addr !=
nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)) { nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
nvgpu_err(g, "%s Error in RPC reply", nvgpu_err(g, "%s Error in RPC reply",
__func__); __func__);
return -1; return -1;
@@ -293,13 +280,11 @@ int gk20a_init_sim_support(struct gk20a *g)
{ {
int err = 0; int err = 0;
u64 phys; u64 phys;
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
/* allocate sim event/msg buffers */ /* allocate sim event/msg buffers */
err = gk20a_alloc_sim_buffer(g, &sim_linux->send_bfr); err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr);
err = err || gk20a_alloc_sim_buffer(g, &sim_linux->recv_bfr); err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr);
err = err || gk20a_alloc_sim_buffer(g, &sim_linux->msg_bfr); err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr);
if (err) if (err)
goto fail; goto fail;
@@ -311,7 +296,7 @@ int gk20a_init_sim_support(struct gk20a *g)
sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
/*write send ring address and make it valid*/ /*write send ring address and make it valid*/
phys = nvgpu_mem_get_addr(g, &sim_linux->send_bfr); phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
sim_writel(g->sim, sim_send_ring_hi_r(), sim_writel(g->sim, sim_send_ring_hi_r(),
sim_send_ring_hi_addr_f(u64_hi32(phys))); sim_send_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_send_ring_r(), sim_writel(g->sim, sim_send_ring_r(),
@@ -328,7 +313,7 @@ int gk20a_init_sim_support(struct gk20a *g)
sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
/*write send ring address and make it valid*/ /*write send ring address and make it valid*/
phys = nvgpu_mem_get_addr(g, &sim_linux->recv_bfr); phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
sim_writel(g->sim, sim_recv_ring_hi_r(), sim_writel(g->sim, sim_recv_ring_hi_r(),
sim_recv_ring_hi_addr_f(u64_hi32(phys))); sim_recv_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_recv_ring_r(), sim_writel(g->sim, sim_recv_ring_r(),

3
drivers/gpu/nvgpu/common/linux/sim.h
View File

@@ -27,9 +27,6 @@ struct sim_gk20a_linux {
struct sim_gk20a sim; struct sim_gk20a sim;
struct resource *reg_mem; struct resource *reg_mem;
void __iomem *regs; void __iomem *regs;
struct nvgpu_mem send_bfr;
struct nvgpu_mem recv_bfr;
struct nvgpu_mem msg_bfr;
}; };
int gk20a_init_sim_support(struct gk20a *g); int gk20a_init_sim_support(struct gk20a *g);

35
drivers/gpu/nvgpu/common/linux/sim_pci.c
View File

@@ -75,12 +75,9 @@ static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
static void gk20a_free_sim_support(struct gk20a *g) static void gk20a_free_sim_support(struct gk20a *g)
{ {
struct sim_gk20a_linux *sim_linux = gk20a_free_sim_buffer(g, &g->sim->send_bfr);
container_of(g->sim, struct sim_gk20a_linux, sim); gk20a_free_sim_buffer(g, &g->sim->recv_bfr);
gk20a_free_sim_buffer(g, &g->sim->msg_bfr);
gk20a_free_sim_buffer(g, &sim_linux->send_bfr);
gk20a_free_sim_buffer(g, &sim_linux->recv_bfr);
gk20a_free_sim_buffer(g, &sim_linux->msg_bfr);
} }
static void gk20a_remove_sim_support(struct sim_gk20a *s) static void gk20a_remove_sim_support(struct sim_gk20a *s)
@@ -91,12 +88,12 @@ static void gk20a_remove_sim_support(struct sim_gk20a *s)
if (sim_linux->regs) if (sim_linux->regs)
sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); sim_writel(s, sim_config_r(), sim_config_mode_disabled_v());
gk20a_free_sim_support(g);
if (sim_linux->regs) { if (sim_linux->regs) {
iounmap(sim_linux->regs); iounmap(sim_linux->regs);
sim_linux->regs = NULL; sim_linux->regs = NULL;
} }
gk20a_free_sim_support(g);
nvgpu_kfree(g, sim_linux); nvgpu_kfree(g, sim_linux);
g->sim = NULL; g->sim = NULL;
@@ -109,8 +106,6 @@ static inline u32 sim_msg_header_size(void)
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va;
@@ -148,8 +143,6 @@ static inline u32 sim_escape_read_hdr_size(void)
static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; cpu_va = (u8 *)sim_linux->send_bfr.cpu_va;
@@ -163,8 +156,6 @@ static int rpc_send_message(struct gk20a *g)
u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
*sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
sim_dma_target_phys_pci_coherent_f() | sim_dma_target_phys_pci_coherent_f() |
@@ -173,7 +164,7 @@ static int rpc_send_message(struct gk20a *g)
sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT);
*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
u64_hi32(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)); u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
@@ -188,8 +179,6 @@ static int rpc_send_message(struct gk20a *g)
static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
{ {
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
u8 *cpu_va; u8 *cpu_va;
cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va;
@@ -200,8 +189,6 @@ static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
static int rpc_recv_poll(struct gk20a *g) static int rpc_recv_poll(struct gk20a *g)
{ {
u64 recv_phys_addr; u64 recv_phys_addr;
struct sim_gk20a_linux *sim_linux =
container_of(g->sim, struct sim_gk20a_linux, sim);
/* Poll the recv ring get pointer in an infinite loop */ /* Poll the recv ring get pointer in an infinite loop */
do { do {
@@ -223,7 +210,7 @@ static int rpc_recv_poll(struct gk20a *g)
(u64)recv_phys_addr_lo << PAGE_SHIFT; (u64)recv_phys_addr_lo << PAGE_SHIFT;
if (recv_phys_addr != if (recv_phys_addr !=
nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)) { nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
nvgpu_err(g, "Error in RPC reply"); nvgpu_err(g, "Error in RPC reply");
return -EINVAL; return -EINVAL;
} }
@@ -320,9 +307,9 @@ int nvgpu_pci_init_sim_support(struct gk20a *g)
sim_linux->regs = l->regs + sim_r(); sim_linux->regs = l->regs + sim_r();
/* allocate sim event/msg buffers */ /* allocate sim event/msg buffers */
err = gk20a_alloc_sim_buffer(g, &sim_linux->send_bfr); err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr);
err = err || gk20a_alloc_sim_buffer(g, &sim_linux->recv_bfr); err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr);
err = err || gk20a_alloc_sim_buffer(g, &sim_linux->msg_bfr); err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr);
if (err) if (err)
goto fail; goto fail;
@@ -334,7 +321,7 @@ int nvgpu_pci_init_sim_support(struct gk20a *g)
sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
/* write send ring address and make it valid */ /* write send ring address and make it valid */
phys = nvgpu_mem_get_addr(g, &sim_linux->send_bfr); phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
sim_writel(g->sim, sim_send_ring_hi_r(), sim_writel(g->sim, sim_send_ring_hi_r(),
sim_send_ring_hi_addr_f(u64_hi32(phys))); sim_send_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_send_ring_r(), sim_writel(g->sim, sim_send_ring_r(),
@@ -351,7 +338,7 @@ int nvgpu_pci_init_sim_support(struct gk20a *g)
sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
/* write send ring address and make it valid */ /* write send ring address and make it valid */
phys = nvgpu_mem_get_addr(g, &sim_linux->recv_bfr); phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
sim_writel(g->sim, sim_recv_ring_hi_r(), sim_writel(g->sim, sim_recv_ring_hi_r(),
sim_recv_ring_hi_addr_f(u64_hi32(phys))); sim_recv_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_recv_ring_r(), sim_writel(g->sim, sim_recv_ring_r(),

5
drivers/gpu/nvgpu/gk20a/sim_gk20a.h
View File

@@ -3,7 +3,7 @@
* *
* GK20A sim support * GK20A sim support
* *
* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,9 @@ struct sim_gk20a {
u32 recv_ring_get; u32 recv_ring_get;
u32 recv_ring_put; u32 recv_ring_put;
u32 sequence_base; u32 sequence_base;
struct nvgpu_mem send_bfr;
struct nvgpu_mem recv_bfr;
struct nvgpu_mem msg_bfr;
void (*remove_support)(struct sim_gk20a *); void (*remove_support)(struct sim_gk20a *);
int (*esc_readl)( int (*esc_readl)(
struct gk20a *g, char *path, u32 index, u32 *data); struct gk20a *g, char *path, u32 index, u32 *data);