diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 08d1a7050..b4404bbea 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -374,6 +374,7 @@ static const struct gops_ltc_intr ga100_ops_ltc_intr = {
 	.isr = ga10b_ltc_intr_isr,
 #ifdef CONFIG_NVGPU_NON_FUSA
 	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+	.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
 #endif
 };
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index aba4cb9a3..af20ec875 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -348,6 +348,7 @@ static const struct gops_ltc_intr ga10b_ops_ltc_intr = {
 	.ltc_intr3_configure_extra = ga10b_ltc_intr3_configure_extra,
 #ifdef CONFIG_NVGPU_NON_FUSA
 	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+	.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
 #endif
 };
 
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
index 8643a8ee0..2990c9117 100644
--- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
@@ -1,7 +1,7 @@
 /*
  * GA10B L2 INTR
  *
- * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -38,5 +38,7 @@ void ga10b_ltc_intr_handle_lts_intr(struct gk20a *g, u32 ltc, u32 slice);
 void ga10b_ltc_intr_handle_lts_intr2(struct gk20a *g, u32 ltc, u32 slice);
 void ga10b_ltc_intr_handle_lts_intr3(struct gk20a *g, u32 ltc, u32 slice);
 void ga10b_ltc_intr_handle_lts_intr3_extra(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
+void ga10b_ltc_intr_handle_illegal_compstat(struct gk20a *g, u32 ltc, u32 slice,
+				u32 ltc_intr, u32 *reg_value);
 
 #endif /* NVGPU_LTC_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
index 4dd28cdf4..3ae3a776d 100644
--- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
@@ -1,7 +1,7 @@
 /*
  * GA10B LTC INTR
  *
- * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -989,6 +989,22 @@ void ga10b_ltc_intr_handle_lts_intr2(struct gk20a *g, u32 ltc, u32 slice)
 			reg_value);
 }
 
+#ifdef CONFIG_NVGPU_NON_FUSA
+void ga10b_ltc_intr_handle_illegal_compstat(struct gk20a *g, u32 ltc, u32 slice,
+		u32 ltc_intr, u32 *reg_value)
+{
+	if ((ltc_intr & ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f()) &&
+		(ltc_intr & ltc_ltcs_ltss_intr_illegal_compstat_m())) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_compstat interrupt",
+			ltc, slice);
+		*reg_value = set_field(*reg_value,
+			ltc_ltcs_ltss_intr_illegal_compstat_m(),
+			ltc_ltcs_ltss_intr_illegal_compstat_reset_f());
+	}
+}
+#endif
+
 void ga10b_ltc_intr_handle_lts_intr(struct gk20a *g, u32 ltc, u32 slice)
 {
 	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
@@ -1036,15 +1052,11 @@ void ga10b_ltc_intr_handle_lts_intr(struct gk20a *g, u32 ltc, u32 slice)
 			ltc_ltcs_ltss_intr_evicted_cb_reset_f());
 	}
 
-	if ((ltc_intr & ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f()) &&
-		(ltc_intr & ltc_ltcs_ltss_intr_illegal_compstat_m())) {
-		nvgpu_log(g, gpu_dbg_intr,
-			"ltc:%d lts: %d illegal_compstat interrupt",
-			ltc, slice);
-		reg_value = set_field(reg_value,
-			ltc_ltcs_ltss_intr_illegal_compstat_m(),
-			ltc_ltcs_ltss_intr_illegal_compstat_reset_f());
+#ifdef CONFIG_NVGPU_NON_FUSA
+	if (g->ops.ltc.intr.handle_illegal_compstat != NULL) {
+		g->ops.ltc.intr.handle_illegal_compstat(g, ltc, slice, ltc_intr, &reg_value);
 	}
+#endif
 
 	if (ltc_intr & ltc_ltcs_ltss_intr_illegal_atomic_m()) {
 		nvgpu_log(g, gpu_dbg_intr,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
index b629d08e7..db41d5fd9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -202,6 +202,8 @@ struct gops_ltc_intr {
 	void (*configure)(struct gk20a *g);
 #ifdef CONFIG_NVGPU_NON_FUSA
 	void (*en_illegal_compstat)(struct gk20a *g, bool enable);
+	void (*handle_illegal_compstat)(struct gk20a *g, u32 ltc, u32 slice,
+			u32 ltc_intr, u32 *reg_value);
 #endif
 	void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
 	void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg);