From b23a114c6343a1114560239b56508e4de0dd6b4f Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 21 Sep 2020 12:19:16 +0530 Subject: [PATCH] gpu: nvgpu: ensure all perfmon writes are complete after reset gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have completed it is necessary to readback each chiplet's PRI fence register. Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this. Implement the HAL for gv11b in new source code file hal/priv_ring/priv_ring_gv11b.c. Bug 2510974 Jira NVGPU-5360 Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453631 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-gpu_hw.yaml | 2 + arch/nvgpu-hal-new.yaml | 4 +- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/Makefile.sources | 3 +- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 4 ++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 4 ++ drivers/gpu/nvgpu/hal/perf/perf_gv11b.c | 4 ++ .../gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c | 39 ++++++++++++ .../gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h | 30 +++++++++ .../gpu/nvgpu/include/nvgpu/gops/priv_ring.h | 3 + .../hw/gv11b/hw_pri_ringstation_fbp_gv11b.h | 63 +++++++++++++++++++ .../hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 1 + .../hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 1 + .../hw/tu104/hw_pri_ringstation_fbp_tu104.h | 63 +++++++++++++++++++ .../hw/tu104/hw_pri_ringstation_gpc_tu104.h | 3 +- .../hw/tu104/hw_pri_ringstation_sys_tu104.h | 3 +- 16 files changed, 225 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h diff --git a/arch/nvgpu-gpu_hw.yaml b/arch/nvgpu-gpu_hw.yaml index fb3173af2..7871451d0 100644 --- a/arch/nvgpu-gpu_hw.yaml +++ b/arch/nvgpu-gpu_hw.yaml @@ -170,6 +170,7 @@ headers: include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h, include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h, include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h, + include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h, include/nvgpu/hw/gv11b/hw_proj_gv11b.h, include/nvgpu/hw/gv11b/hw_pwr_gv11b.h, include/nvgpu/hw/gv11b/hw_ram_gv11b.h, @@ -209,6 +210,7 @@ headers: include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h, include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h, include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h, + include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h, include/nvgpu/hw/tu104/hw_proj_tu104.h, include/nvgpu/hw/tu104/hw_psec_tu104.h, include/nvgpu/hw/tu104/hw_pwr_tu104.h, diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 3f6fe145c..8e54c7aa2 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -88,7 +88,9 @@ priv_ring_fusa: priv_ring: safe: no owner: Seema K - sources: [ hal/priv_ring/priv_ring_gm20b.c ] + sources: [ hal/priv_ring/priv_ring_gm20b.c, + hal/priv_ring/priv_ring_gv11b.c, + hal/priv_ring/priv_ring_gv11b.h ] ptimer_fusa: safe: yes diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 08f8b0b64..9b23f725c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -363,7 +363,8 @@ nvgpu-y += \ hal/pmu/pmu_tu104.o \ hal/top/top_gp106.o \ hal/top/top_gp10b.o \ - hal/tpc/tpc_gv11b.o + hal/tpc/tpc_gv11b.o \ + hal/priv_ring/priv_ring_gv11b.o # Linux specific parts of nvgpu. nvgpu-y += \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index f9a86ec1b..fdb94a25f 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -391,7 +391,8 @@ endif ifeq ($(CONFIG_NVGPU_PROFILER),1) srcs += common/profiler/profiler.c \ - common/profiler/pm_reservation.c + common/profiler/pm_reservation.c \ + hal/priv_ring/priv_ring_gv11b.c endif ifeq ($(CONFIG_NVGPU_KERNEL_MODE_SUBMIT),1) diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index e559d65b6..1d448371a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -62,6 +62,7 @@ #include "hal/class/class_gv11b.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" +#include "hal/priv_ring/priv_ring_gv11b.h" #include "hal/gr/config/gr_config_gv100.h" #include "hal/power_features/cg/gv11b_gating_reglist.h" #ifdef CONFIG_NVGPU_COMPRESSION @@ -1335,6 +1336,9 @@ static const struct gops_priv_ring gv11b_ops_priv_ring = { .enum_ltc = gm20b_priv_ring_enum_ltc, .get_gpc_count = gm20b_priv_ring_get_gpc_count, .get_fbp_count = gm20b_priv_ring_get_fbp_count, +#ifdef CONFIG_NVGPU_PROFILER + .read_pri_fence = gv11b_priv_ring_read_pri_fence, +#endif }; static const struct gops_fuse gv11b_ops_fuse = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index b14fa6ec0..e30644ed5 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -48,6 +48,7 @@ #include "hal/class/class_tu104.h" #include "hal/priv_ring/priv_ring_gm20b.h" #include "hal/priv_ring/priv_ring_gp10b.h" +#include "hal/priv_ring/priv_ring_gv11b.h" #include "hal/power_features/cg/tu104_gating_reglist.h" #include "hal/cbc/cbc_gm20b.h" #include "hal/cbc/cbc_tu104.h" @@ -1428,6 +1429,9 @@ static const struct gops_priv_ring tu104_ops_priv_ring = { .enum_ltc = gm20b_priv_ring_enum_ltc, .get_gpc_count = gm20b_priv_ring_get_gpc_count, .get_fbp_count = gm20b_priv_ring_get_fbp_count, +#ifdef CONFIG_NVGPU_PROFILER + .read_pri_fence = gv11b_priv_ring_read_pri_fence, +#endif }; #endif diff --git a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c index 6b36fd96e..28cf07e37 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c +++ b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c @@ -472,6 +472,10 @@ void gv11b_perf_reset_hwpm_pmm_registers(struct gk20a *g) g->ops.perf.get_pmmgpc_per_chiplet_offset(), g->num_gpc_perfmon); } + + if (g->ops.priv_ring.read_pri_fence != NULL) { + g->ops.priv_ring.read_pri_fence(g); + } } void gv11b_perf_init_hwpm_pmm_register(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c new file mode 100644 index 000000000..6f3522622 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "priv_ring_gv11b.h" + +#include +#include +#include + +void gv11b_priv_ring_read_pri_fence(struct gk20a *g) +{ + /* Read back to ensure all writes to all chiplets are complete. */ + nvgpu_readl(g, pri_ringstation_sys_pri_fence_r()); + nvgpu_readl(g, pri_ringstation_gpc_pri_fence_r()); + nvgpu_readl(g, pri_ringstation_fbp_pri_fence_r()); +} + diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h new file mode 100644 index 000000000..87fd5c766 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_PRIV_RING_GV11B_H +#define NVGPU_PRIV_RING_GV11B_H + +#ifdef CONFIG_NVGPU_PROFILER +struct gk20a; +void gv11b_priv_ring_read_pri_fence(struct gk20a *g); +#endif + +#endif /* NVGPU_PRIV_RING_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h index a8cbb88ef..ce047c3ec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h @@ -141,6 +141,9 @@ struct gops_priv_ring { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ void (*decode_error_code)(struct gk20a *g, u32 error_code); +#ifdef CONFIG_NVGPU_PROFILER + void (*read_pri_fence)(struct gk20a *g); +#endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NEXT) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h new file mode 100644 index 000000000..0f1c1d32d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function/Macro naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef NVGPU_HW_PRI_RINGSTATION_FBP_GV11B_H +#define NVGPU_HW_PRI_RINGSTATION_FBP_GV11B_H + +#include +#include + +#define pri_ringstation_fbp_pri_fence_r() (0x001241fcU) +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index 8acef04a5..ae1393e43 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -69,4 +69,5 @@ #define pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(r)\ (((r) >> 20U) & 0x3U) #define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) +#define pri_ringstation_gpc_pri_fence_r() (0x001281fcU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index 58b5a7e9f..1b18d13ea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -72,4 +72,5 @@ #define pri_ringstation_sys_priv_error_info_priv_level_v(r)\ (((r) >> 20U) & 0x3U) #define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) +#define pri_ringstation_sys_pri_fence_r() (0x001221fcU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h new file mode 100644 index 000000000..dc7b7de38 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function/Macro naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef NVGPU_HW_PRI_RINGSTATION_FBP_TU104_H +#define NVGPU_HW_PRI_RINGSTATION_FBP_TU104_H + +#include +#include + +#define pri_ringstation_fbp_pri_fence_r() (0x001241fcU) +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h index 312099a35..675622b4a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -63,4 +63,5 @@ #define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) #define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) #define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) +#define pri_ringstation_gpc_pri_fence_r() (0x001281fcU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h index 09b20240d..d85d96298 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -67,4 +67,5 @@ #define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) #define pri_ringstation_sys_priv_error_info_r() (0x00122128U) #define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) +#define pri_ringstation_sys_pri_fence_r() (0x001221fcU) #endif