gpu: nvgpu: move mc_boot_0 function to hals and rename to get_chip_details

This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.

JIRA NVGPU-2524

Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226018
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -46,7 +46,7 @@
 
 bool is_nvgpu_gpu_state_valid(struct gk20a *g)
 {
-	u32 boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL);
+	u32 boot_0 = g->ops.mc.get_chip_details(g, NULL, NULL, NULL);
 
 	if (boot_0 == 0xffffffffU) {
 		nvgpu_err(g, "GPU has disappeared from bus!!");

drivers/gpu/nvgpu/common/mc/mc.c

@@ -22,36 +22,9 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
 
-#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
-
-u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
-{
-	u32 val = nvgpu_readl_impl(g, mc_boot_0_r());
-
-	if (val != U32_MAX) {
-
-		if (arch != NULL) {
-			*arch = mc_boot_0_architecture_v(val) <<
-				NVGPU_GPU_ARCHITECTURE_SHIFT;
-		}
-
-		if (impl != NULL) {
-			*impl = mc_boot_0_implementation_v(val);
-		}
-
-		if (rev != NULL) {
-			*rev = (mc_boot_0_major_revision_v(val) << 4) |
-				mc_boot_0_minor_revision_v(val);
-		}
-	}
-
-	return val;
-}
-
 /**
  * cyclic_delta - Returns delta of cyclic integers a and b.
  *

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -958,6 +958,7 @@ static const struct gpu_ops gm20b_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = gm20b_get_chip_details,
 		.intr_mask = gm20b_mc_intr_mask,
 		.intr_enable = gm20b_mc_intr_enable,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -1054,6 +1054,7 @@ static const struct gpu_ops gp10b_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = gm20b_get_chip_details,
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gp10b_intr_enable,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1257,6 +1257,7 @@ static const struct gpu_ops gv11b_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = gm20b_get_chip_details,
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gv11b_intr_enable,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/hal/init/hal_init.c

@@ -36,6 +36,8 @@
 #include "hal_tu104.h"
 #endif
 
+#include "hal/mc/mc_gm20b.h"
+
 int nvgpu_init_hal(struct gk20a *g)
 {
 	int err = 0;
@@ -97,9 +99,10 @@ int nvgpu_detect_chip(struct gk20a *g)
 		return 0;
 	}
 
-	boot_0 = nvgpu_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev);
+	boot_0 = gm20b_get_chip_details(g, &p->gpu_arch,
+					&p->gpu_impl, &p->gpu_rev);
 	if (boot_0 == U32_MAX) {
-		nvgpu_err(g, "nvgpu_mc_boot_0 failure!");
+		nvgpu_err(g, "get_chip_details failure!");
 		return -ENODEV;
 	}
 

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1274,6 +1274,7 @@ static const struct gpu_ops tu104_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = gm20b_get_chip_details,
 		.intr_enable = intr_tu104_enable,
 		.intr_mask = intr_tu104_mask,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/hal/mc/mc_gm20b.h

@@ -32,6 +32,8 @@
 struct gk20a;
 enum nvgpu_unit;
 
+u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
+
 u32  gm20b_mc_isr_nonstall(struct gk20a *g);
 void gm20b_mc_enable(struct gk20a *g, u32 units);
 void gm20b_mc_disable(struct gk20a *g, u32 units);

drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c

@@ -37,6 +37,30 @@
 
 #include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
 
+u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
+{
+	u32 val = nvgpu_readl_impl(g, mc_boot_0_r());
+
+	if (val != U32_MAX) {
+
+		if (arch != NULL) {
+			*arch = mc_boot_0_architecture_v(val) <<
+				NVGPU_GPU_ARCHITECTURE_SHIFT;
+		}
+
+		if (impl != NULL) {
+			*impl = mc_boot_0_implementation_v(val);
+		}
+
+		if (rev != NULL) {
+			*rev = (mc_boot_0_major_revision_v(val) << 4) |
+				mc_boot_0_minor_revision_v(val);
+		}
+	}
+
+	return val;
+}
+
 u32 gm20b_mc_isr_nonstall(struct gk20a *g)
 {
 	u32 ops = 0U;

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c

@@ -751,6 +751,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = NULL,
 		.intr_mask = NULL,
 		.intr_enable = NULL,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -873,6 +873,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	},
 #endif
 	.mc = {
+		.get_chip_details = NULL,
 		.intr_mask = NULL,
 		.intr_enable = NULL,
 #ifdef CONFIG_NVGPU_LS_PMU

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1146,9 +1146,6 @@ int gk20a_do_idle_impl(struct gk20a *g, bool force_reset);
 int gk20a_do_unidle_impl(struct gk20a *g);
 #endif
 
-/** Bit offset of the Architecture field in the HW version register */
-#define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
-
 /**
  * Constructs unique and compact GPUID from nvgpu_gpu_characteristics
  * arch/impl fields.

drivers/gpu/nvgpu/include/nvgpu/gops_mc.h

@@ -38,6 +38,40 @@ struct gk20a;
  * @see gpu_ops.
  */
 struct gops_mc {
+	/**
+	 * @brief Get the GPU architecture, implementation and revision.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 * @param arch [out]	The GPU architecture level. Can be passed as
+	 *			NULL if not needed by the caller.
+	 * @param impl [out]	The implementation of the GPU architecture.
+	 *			Can be passed as NULL if not needed by the
+	 *			caller.
+	 * @param rev [out]	The revision of the chip. Can be passed as
+	 *			NULL if not needed by the caller.
+	 *
+	 * This function is invoked to get the GPU architecture, implementation
+	 * and revision level of the GPU chip before #nvgpu_finalize_poweron.
+	 * These values are used for chip specific SW/HW handling in the
+	 * driver.
+	 *
+	 * Steps:
+	 * - Read the register mc_boot_0_r().
+	 * - If value is not #U32_MAX
+	 *   - Set in \a arch, the value obtained by mc_boot_0_architecture_v()
+	 *     of the read value shifting left by #NVGPU_GPU_ARCHITECTURE_SHIFT.
+	 *   - Set in \a impl, the value obtained by
+	 *     mc_boot_0_implementation_v() of the read value.
+	 *   - Set in \a rev, value obtained by shifting left
+	 *     mc_boot_0_major_revision_v() of the read value by 4 OR'ing with
+	 *     mc_boot_0_minor_revision_v() of the value.
+	 * - return the value of the register mc_boot_0_r read.
+	 *
+	 * @return value read from mc_boot_0_r().
+	 */
+	u32 (*get_chip_details)(struct gk20a *g,
+				u32 *arch, u32 *impl, u32 *rev);
+
 	/**
 	 * @brief Clear the GPU device interrupts at master level.
 	 *

drivers/gpu/nvgpu/include/nvgpu/mc.h

@@ -46,6 +46,9 @@ enum nvgpu_unit {
 #endif
 };
 
+/** Bit offset of the Architecture field in the HW version register */
+#define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
+
 #define NVGPU_MC_INTR_STALLING		0U
 #define NVGPU_MC_INTR_NONSTALLING	1U
 
@@ -53,7 +56,6 @@ enum nvgpu_unit {
 #define NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE	BIT32(0)
 #define NVGPU_NONSTALL_OPS_POST_EVENTS		BIT32(1)
 
-u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
 void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
 
 #endif

userspace/units/init/nvgpu-init.c

@@ -559,8 +559,8 @@ struct unit_module_test init_tests[] = {
 	UNIT_TEST(init_setup_env,			test_setup_env,		NULL, 0),
 	UNIT_TEST(init_can_busy,			test_can_busy,		NULL, 0),
 	UNIT_TEST(init_get_put,				test_get_put,		NULL, 0),
-	UNIT_TEST(init_check_gpu_state,			test_check_gpu_state,	NULL, 0),
 	UNIT_TEST(init_hal_init,			test_hal_init,		NULL, 0),
+	UNIT_TEST(init_check_gpu_state,			test_check_gpu_state,	NULL, 0),
 	UNIT_TEST(init_poweron,				test_poweron,		NULL, 0),
 	UNIT_TEST(init_poweron_branches,		test_poweron_branches,	NULL, 0),
 	UNIT_TEST(init_poweroff,			test_poweroff,		NULL, 0),